A novel BRAM content accessing and processing method based on FPGA configuration bitstream |
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| Affiliation: | 1. Dept. of Electronics, University of the Basque Country UPV/EHU, Alameda Urquijo S/N, 48013 Bilbao, Spain;2. OPTIMA Unit. TECNALIA. P. Tecnologico Bizkaia, Ed. 700, 48160 Derio, Spain;3. Dept. of Communications Engineering, University of the Basque Country UPV/EHU, Alameda Urquijo S/N, 48013 Bilbao, Spain;1. Madeira Interactive Technologies Institute, Funchal, Portugal;2. University of Madeira, Funchal, Portugal;3. University of Las Palmas de Gran Canaria, Las Palmas de Gran Canaria, Spain;1. Computer Systems Laboratory, Department of Computer Engineering, Chosun University, Dongku SeoSuk Dong 375, Gwangju City, 501-759, South Korea;2. Department of Mathematical Sciences (Computer Science), Faculty of Science, Abubakar Tafawa Balewa University (Federal University of Technology) ATBU, Yelwa Campus, Dass Road, P.M.B. 0248, Bauchi State, Nigeria;1. Department of Computer, Faculty of Engineering, Persian Gulf University, Bushehr, Iran;2. Department of Electrical Engineering and Computer Science, University of Central Florida, Orlando, USA;3. Department of Computer Engineering, Beyza Branch, Islamic Azad University, Beyza, Iran;4. School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Tehran, Iran;1. Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, USA;2. Department of Computer Science, University of Pittsburgh, Pittsburgh, USA |
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| Abstract: | This paper presents a new approach to manage data content of memories implemented in FPGAs through the configuration bitstream. The proposed approach is able to read and write the data content from Block RAMs (BRAMs) in FPGA based designs by reading and processing the information stored in the bitstream. Thanks to this method it is possible to extract, load, copy or compare the information of BRAMs without neither resource overhead nor performance penalty in the design. It can also be applied to existing designs without the need of re-synthesizing. Due to its advantages it becomes an interesting tool to carry out several applications, such as error detection and recovery or fault injection. It also opens the doors to the design of cutting-edge applications. The approach has been implemented in a Xilinx ZYNQ System-on-Chip (SoC) device, which combines an FPGA and an ARM9 microprocessor. The access to the configuration bitstream has been performed using the ZYNQ’s Processor Configuration Access Port (PCAP). Nevertheless, the flow presented in this article can be adapted to devices from other Xilinx families or vendors. The proposed approach has been fully tested and compared with specifically designed memory controllers. The results obtained in the experimental tests confirm that the proposed approach works properly without increasing the resource overhead but at a penalty in terms of processing time. |
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