Efficiency modeling and exploration of 64-bit ARM compute nodes for exascale |
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| Affiliation: | 1. Bull atos technologies, Les Clayes Sous Bois, France;2. LEAT, CNRS UMR7248, University of Nice Sophia Antipolis, France;1. Guangxi Key Lab of Multi-Source Information Mining & Security, Faculty of Electronic Engineering, Guangxi Normal University, Guilin, 541004, China;2. School of Computing and Intelligent Systems, Ulster University, Derry, BT48 7JL, UK;1. Department of Computer, Abadan Branch, Islamic Azad University, Abadan, Iran;2. Department of Computer Engineering, Yadegar -e- Imam Khomeini (RAH) Shahre Rey Branch, Islamic Azad University, Tehran, Iran;3. Institute for Integrated Circuits, Johannes Kepler University Linz, Austria;1. Digital IC dEsign and Systems Lab (DICES Lab), Technological Educational Institute of Western Greece, Greece;2. Industrial System Institute (ISI), “Athena” Research Center, Patras, Greece;3. SBA Research, Vienna, Austria;1. DTU Compute Dept, Technical University of Denmark, Kgs. Lyngby, Denmark;2. Alten Sverige AB, Kista, Sweden;3. School of Innovation, Design, and Engineering, Mälardalen University, Västerås, Sweden |
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| Abstract: | This paper investigates the use of 64-bit ARM cores to improve the processing efficiency of upcoming HPC systems. It describes a set of available tools, models and platforms, and their combination in an efficient methodology for the design space exploration of large manycore computing clusters. Experimentations and results using representative benchmarks allow to set an exploration approach to evaluate essential design options at micro-architectural level while scaling with a large number of cores. We then apply this methodology to examine the validity of SoC partitioning as an alternative to using large SoC designs based on coherent multi-SoC models and the proposed SoC Coherent Interconnect (SCI). |
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