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Accelerated Techniques in Stem Fault Simulation
引用本文:Shi Yin,Wei Daozheng. Accelerated Techniques in Stem Fault Simulation[J]. 计算机科学技术学报, 1996, 11(6): 551-561. DOI: 10.1007/BF02951618
作者姓名:Shi Yin  Wei Daozheng
作者单位:[1]CADLaboratory,InstituteofComputingTechnology,ChineseAcademyofSciencesBeijing100080 [2]CADLaboratory,Inst
摘    要:In order to cope with the most expensive stem fault simulation in fault simulation field.several accelerated techniques are presented in this paper.These techniques include static analysis on circuit structure in preprocessing stage and dynamic calculations in fault simulation stage.With these techniques,the area for stem for stem fault simulation and number of the stems requiring explicit fault simulation are greatly reduced,so that the entire fault simulation time is substantially decreased.Experimental results given in this paper show that the fault simulation algorithm using these techniques is of very high efficiency for both small and large numbers of test patterns.Especially with the increase of circuit gates,its effectiveness improves obviously.

关 键 词:晶体管 管座 故障模拟 临界路径跟踪

Accelerated techniques in stem fault simulation
Yin Shi,Daozheng Wei. Accelerated techniques in stem fault simulation[J]. Journal of Computer Science and Technology, 1996, 11(6): 551-561. DOI: 10.1007/BF02951618
Authors:Yin Shi  Daozheng Wei
Affiliation:CAD Laboratory; Institute of Computing Technology; Chinese Academy of SciencesBeijing 100080;
Abstract:In order to cope with the most expensive stem fault simulation in fault simu-lation field, several accelerated techniques are presented in this paper. These techniques include static analysis on circuit structure in preprocessing stage and dynamic calculations in fault simulation stage. With these techniques,the area for stem fault simulation and number of the stems requiring explicit fault simulation are greatly reduced, so that the entire fault simulation time is substantially decreased. Experimental results given in this paper show that the fault simulation algorithm using these techniques is of very high efficiency for both small and large numbers of test patterns. Especially with the increase of circuit gates, its effectivenbss improves obyiously.
Keywords:Fault simulation   critical path tracing   parallel pattern evaluation   stem fault simulation   explicit fault simulation
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