| IDDT: Fundamentals and Test Generation |
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| 作者姓名： | 邝继顺 尤志强 朱启建 闵应骅 |
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| 作者单位： | [1]CollegeofComputerandCommunication,HunanUniversity,Changsha410082,P.R.China [2]InstituteofComputingTechnology,TheChineseAcademyofSciences,Beijing100080,P.R.China |
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| 基金项目： | This work was supported by the National Natural Science Foundation of China under Grant No.60173042. |
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| 摘 要： | It is the time to explore the fundamentals of IDDT testing when extensive work has been done for IDDT testing since it was proposed.This paper precisely defines the concept of average transient current(IDDT) of CMOS digital ICs,and experimentally analyzes the feasibility of IDDT test generation at gate level.Based on the SPICE simulation results,the paper suggests a formula to calculate IDDT by means of counting only logical up-transitions,which enables IDDT test generation at logic level.The Bayesian optimization algorithm is utilized for IDDT test generation.Experimental results show that about 25% stuck-open faults are with IDDT testability larger than 2.5,and likely to be IDDT testable.It is also found that most IDDT testable faults are located near the primary inputs of a circuit under test.IDDT test generation does not require fault sensitization procedure compared with stuck-at fault test generation.Furthermore,some redundant stuck-at faults can be detected by using IDDT testing.
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| 关 键 词： | IDDT 测试生成 逻辑转变 固定开路故障 CMOS |
| 收稿时间： | 8 July 2005 |
IDDT: Fundamentals and Test Generation |
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| Jishun Kuang, ZhiQiang You, QiJian Zhu and YingHua Min.IDDT: Fundamentals and Test Generation[J].Journal of Computer Science and Technology,2003,18(3):0-0. |
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| Authors: | Jishun Kuang ZhiQiang You QiJian Zhu and YingHua Min |
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| Affiliation: | (1) College of Computer and Communication, Hunan University, 410082 Changsha, P. R. China;(2) Institute of Computing Technology, The Chinese Academy of Sciences, 100080 Beijing, P.R. China |
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| Abstract: | It is the time to explore the fundamentals of IDDT testing when extensive work has been done for IDDT testing since it was proposed. This paper precisely defines the concept of average transient current (iDDT) of CMOS digital ICs, and experimentally analyzes the feasibility of IDDT test generation at gate level. Based on the SPICE simulation results, the paper suggests a formula to calculate IDDT by means of counting only logical up-transitions, which enables IDDT test generation at logic level. The Bayesian optimization algorithm is utilized for IDDT test generation. Experimental results show that about 25% stuck-open faults are with IDDT testability larger than 2.5, and likely to be IDDT testable. It is also found that most IDDT testable faults are located near the primary inputs of a circuit under test. IDDT test generation does not require fault sensitization procedure compared with stuck-at fault test generation. Furthermore, some redundant stuck-at faults can be detected by using IDDT testing. |
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| Keywords: | IDDT testing logical transition hazard stuck-open fault |
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