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Trace Software Pipelining
作者姓名:Wang Jian  Andreas Krall  M.Anton Ertl
作者单位:[1]InstitutefurComputersprachen,TechnischeUniversitatWien,Argentinierstr.8A-1040Vienna,Austria [2]Institute,TechnischeUniversitatWien,Argentinierstr.8A-1040Vienna,Austria
摘    要:Global software pipelining is a complex but efficient compilation technique to exploit instruction-level parallelism for loops with branches.This paper presents a novel global software pipelining technique,called Trace Software Pipelining,targeted to the instruction-level parallel processors such as Very Long Instruction Word (VLIW) and superscalar machines.Trace software pipelining applies a global code scheduling technique to compact the original loop body.The resulting loop is called a trace software pipelined (TSP) code.The trace softwrae pipelined code can be directly executed with special architectural support or can be transformed into a globally software pipelined loop for the current VLIW and superscalar processors.Thus,exploiting parallelism across all iterations of a loop can be completed through compacting the original loop body with any global code scheduling technique.This makes our new technique very promising in practical compilers.Finally,we also present the preliminary experimental results to support our new approach.

关 键 词:软件  软件流水线操作  有效编码技术

Trace software pipelining
Wang Jian,Andreas Krall,M.Anton Ertl.Trace Software Pipelining[J].Journal of Computer Science and Technology,1995,10(6):481-490.
Authors:Jian Wang  Andreas Krall  M Anton Ertl
Affiliation:Institut fur Computersprachen; Technische Universitat Wien; Argentinierstr. 8A-1040 Vienna; Austria;
Abstract:Global software pipelining is a complex but efficient compilation technique to exploit instruction-level parallelism for loops with branches. This paper presents a novel global software pipelining technique, called Thace Software Pipelining,targeted to the instruction-level parallel processors such as Very Long Instruc-tion Word (VLIW) and superscalar machines. Thace software pipelining applies a global code scheduling technique to compact the original loop body. The re-sulting loop is called a trace software pipelined (TSP) code. The trace softwrae pipelined code can be directly executed with special architectural support or call be transformed into a globally software pipelined loop for the current VLIW and superscalar processors. Thus, exploiting parallelism across all iterations of a loop can be completed through compacting the original loop body with any global code scheduling technique. This makes our new technique very promis-ing in practical compilers. Finally, we also present the preliminary experimental results to support our new approach.
Keywords:Instruction-level parallelism  fine-grain parallelism  software pipelining  loop scheduling  Very Long Instruction Word (VLIW)  superscalar processor
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