On the realization of multimemory block structure digital adaptive filter using distributed arithmetic

Abstract

In this paper, the hardware complexity and system performance of the two multimemory structures (parallel and cascade) of adaptive digital filters are studied. These structures are based on the use of a distributed arithmetic technique without a multiplier in the realization of the filter function. The results from computer simulations and implementations by an MC 68000 16‐bit microprocessor demonstrate that adaptive filters implemented by these two structures have comparable performances on the average. However, the hardware implementation of the parallel structure is simpler and can achieve higher operation speed with fewer IC components. A prototype of a 16‐tap parallel structure (divided into two blocks) adaptive filter is implemented by Schottky TTL circuits. Experimental result of this adaptive filter for noise cancellation has demonstrated its capability for high speed signal processing.