基于田口法的CSP器件结构优化设计

为提高芯片尺寸封装(CSP)器件的焊点可靠性，基于田口法，采用Garofalo-Arrhenius稳态本构方程和有限元法，对CSP器件焊点热循环载荷下的应力应变分布进行有限元模拟. 考虑焊点材料、焊点高度、芯片厚度、基板厚度四个控制因素，借助田口法，采用正交表L9(34)安排试验，研究发现影响焊点可靠性的主要影响因素为焊点材料和焊点高度. 经过田口试验法优化得到的最佳方案组合为焊点材料Sn3.9Ag0.6Cu，焊点高度0.29 mm，芯片厚度0.1 mm，基板厚度0.17 mm. 该最优方案和原始设计方案相比，蠕变应变能密度降低65.4%，信噪比提高了9.22 dB. 结果表明，CSP器件焊点可靠性得到显著提高.

Structure optimization design of CSP device based on Taguchi method

In order to improve the solder joint reliability of chip scale package (CSP) devices, based on the Taguchi method, the stress-strain distributions of the CSP device under thermal cycling are simulated by using the steady-state constitutive equations of Garofalo-Arrhenius and the finite element method. Considering the solder joint material, solder joint height, chip thickness and the thickness of the substrate four factors, using Taguchi method and orthogonal table L9(34) to arrange the experiment, the study found that the main influencing factors of solder joint reliability are the solder joint material and the height of solder joints. Optimized by Taguchi method, the best combination of materials is solder material Sn3.9Ag0.6Cu, solder joint height 0.29 mm, chip thickness 0.1 mm and substrate thickness 0.17 mm. Compared with the original design scheme, the optimal scheme reduces the creep strain energy density by 65.4% and the signal-to-noise ratio by 9.22 dB. The results show that the reliability of CSP solder joints is significantly improved.