基于FPGA+DSP架构异步FIFO视频图像数据采集实现

针对 FPGA 资源紧张和数据在不同时钟域间传递的亚稳态问题，设计一种基于 FPGA+DSP 架构的异步FIFO视频图像数据采集方法。在IIC配置模块和解交织模块的作用下，通过在2个时钟域的交界处设计3个低深度异步FIFO方式实现视频数据流的传输，由发送时钟域将数据写入，接收时钟域将数据读出，在数据传输的同时实现数据的缓存；通过分析 FPGA 芯片内资源利用情况并进行系统测试，结果表明：系统能够准确地再现输入的视频图像，实现视频图像数据的实时采集。

Realization Video-image-data Acquisition and Accomplish Based on FPGA+DSP Framework Asynchronous FIFO

For those FPGA chips which lack of internal storage resource and the metastability problem that the data transferred between the different clock domains. A method was designed to acquire the video image data based on FPGA+DSP framework. Under the effect of IIC configuration module and de-interleave module, by through desiring 3 lower depth asynchronous FIFO realized video-data stream’s transfer between the different clock domain, the data written into FIFO at send clock domain and read at received clock domain, it realized the data transfer and acquire simultaneously. By analysis the utilization of the FPGA chip resource and carry on a system test, the result of test have shown that the system can accurately re-appear the input video image and realize the real time video data acquisition.