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基于载波锁频锁相联合跟踪的数字中频接收机环路设计
引用本文:王光鼎,游福初,房建成.基于载波锁频锁相联合跟踪的数字中频接收机环路设计[J].战术导弹技术,2012(3):1-7,12.
作者姓名:王光鼎  游福初  房建成
作者单位:中国航天科工集团三院303所;北京航空航天大学
摘    要:介绍了接收卫星信号的数字中频接收机载波同步跟踪关键技术,针对高机动环境下载波同步需要解决的捕获带宽、捕获速度与跟踪精度的矛盾,综合利用了传统数字锁频环路(DFLL)和数字锁相环路(DPLL)的优点,设计了一种适合高机动环境下数字中频接收机的锁频联合锁相环工作的环路方案。并利用计算机仿真分析结果,证明了该方案的可行性和优越性,为ADC+FPGA+DSP框架下卫星信号数字中频接收机软硬件实现提供了设计依据。

关 键 词:卫星信号数字中频接收机  数字三阶锁相环路  数字二阶锁频环路  数字锁频锁相跟踪环

Loop Design of Digital Intermediate Frequency Receiving Machine Based on Carrier Track Technique of Frequency Lock Associated with Phase Lock
Wang Guangding,You Fuchu,Fang Jiancheng.Loop Design of Digital Intermediate Frequency Receiving Machine Based on Carrier Track Technique of Frequency Lock Associated with Phase Lock[J].Tactical Missile Technology,2012(3):1-7,12.
Authors:Wang Guangding  You Fuchu  Fang Jiancheng
Affiliation:1.The 303th Institute of the Third Research Academy,CASIC,Beijing 100074,China; 2.Beijing University of Aeronautics and Astronautics,Beijing 100191,China)
Abstract:The carrier synchronization track technique of digital intermediate frequency receiving machine is introduced,which is important for receiving the signal of satellites.In the seriously dynamic situation,the inconsistency among the bandwidth,velocity and precision of capture for carrier synchronization should be resolved.Integrating the traditional FDLL and DPLL,a new loop project is designed,which frequency lock associated with phase lock,and it’s suitable for digital intermediate frequency receiving machine in seriously dynamic situation.The analysis and simulation by computer is carried out,and the feasibility and advantage are proved.Then the hardware framework with ADC+FPGA+DSP for digital intermediate frequency receiving machine of satellite signal is well-founded.
Keywords:digital intermediate frequency receiving machine of satellite signal  three-rank digital phase lock loop  two-rank digital frequency lock loop  digital frequency lock associated with phase lock loop
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