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| 基于FPGA的VME总线控制器及其驱动程序 | |
| 引用本文： | 徐杨,乔卫民,赵中,王国强.基于FPGA的VME总线控制器及其驱动程序[J].核电子学与探测技术,2007,27(6):1064-1066,1069. |
| 作者姓名： | 徐杨 乔卫民 赵中 王国强 |
| 作者单位： | 1. 中国科学院近代物理研究所,甘肃,兰州,730000;中国科学院高能物理研究所,北京,100039 2. 中国科学院近代物理研究所,甘肃,兰州,730000 3. 中国科学院研究生院,北京,100039 4. 黄淮学院计算机科学系,驻马店市,463000 |
| 摘 要： | 本文论述了用于兰州重离子加速器冷却储存环(HIRFL-CSR)前端控制系统的总线控制器的FPGA设计及其基于ARM-Linux下的驱动程序设计.该总线控制器采用Altera公司的ACEX系列中的EP1K30实现,通过VME总线背板同其它VME设备(CPLD)通信,可读VME设备数据,监视电源运行状况,也可向VME设备发送命令和写数据,并且能够响应VME设备中断,读中断数据.为了能够通过AT91RM9200控制器访问VME总线控制器,必须为其编写相应的驱动程序.驱动程序定义了应用程序调用接口和数据格式,并实现了中断机制、多进程访问和数据的突发(burst)读写. |
| 关 键 词： | AT91RM9200 驱动程序 FPGA VME |
| 文章编号： | 0258-0934（2007）06-1064-03 |
| 收稿时间： | 2007-03-08 |
| 修稿时间： | 2007年3月8日 |
The VME Bus Controller Based On FPGA and Its Device Driver |
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| XU Yang,QIAO Wei-min,ZHAO Zhong,WANG Guo-qiang.The VME Bus Controller Based On FPGA and Its Device Driver[J].Nuclear Electronics & Detection Technology,2007,27(6):1064-1066,1069. | |
| Authors: | XU Yang QIAO Wei-min ZHAO Zhong WANG Guo-qiang |
| Abstract: | This article introduces a VME Bus Controller of front control system of HIRFL-CSR. It is implemented by FPGA which is EP1K30 of ACEX family of Altera Corporation. It communicates with other VME device through VME backplane. It is able to accept data from VME device and watch status of magnet power supply. Besides sending command and data to VME device, it is also able to respond interrupt and read interrupt data. We also need to write a device driver for VME Bus Controller in order to be accessible by AT91RM9200. The device driver defines some APIs and data format for application, implements multi-process access and burst read-write, as well as interrupt mechanism. |
| Keywords: | AT91RM9200 Device Driver FPGA VME |
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