65 nm双阱CMOS静态随机存储器多位翻转微束及宽束实验研究

利用微束和宽束辐照装置分别对两款65 nm双阱CMOS静态随机存储器(SRAM)进行重离子垂直辐照实验，将多位翻转（multiple-cell upset, MCU）类型、位置、事件数与器件结构布局相结合对单粒子翻转（single-event upset, SEU）的截面、MCU机理进行深入分析。结果表明，微束束斑小且均匀性好，不存在离子入射外围电路的情况；NMOS晶体管引发的MCU与总SEU事件比值高达32%，NMOS晶体管间的电荷共享不可忽略；实验未测得PMOS晶体管引发的MCU，高密度阱接触能有效抑制PMOS晶体管间的电荷共享；减小晶体管漏极与N阱/P阱界面的间距能降低SRAM器件SEU发生概率；减小存储单元内同类晶体管漏极间距、增大存储单元间同类晶体管漏极间距，可减弱电荷共享，从而减小SRAM器件MCU发生概率。

Micro-beam and Broad-beam Experimental Research of Multiple-cell Upset in 65 nm Dual-well CMOS SRAM

The heavy-ion micro-beam experiment and broad-beam experiment were performed in two 65 nm dual-well CMOS static random access memories (SRAMs) in normal incident angle, respectively. Single event upset (SEU) cross section and the main physical mechanisms of multiple-cell upset (MCU) were investigated by combining MCU pattern, position and counts with the memory cell array layout. The results show that the micro-beam spot is small and uniform, which makes sure that the ions do not hit the peripheral circuits. The ratio of MCU caused by NMOS transistor and the total SEU events is up to 32%, which indicates the charge sharing between NMOS transistors can not be ignored, while there’s no MCU caused by PMOS transistor during the tests, which infers that the high density well contact can inhibit the charge sharing between PMOS transistors effectively. Moreover, reducing the spacing between the drain and the N-well/P-well interface can lessen the probability of SEU. While reducing the spacing between the same kind of transistors in a memory cell as well as increasing the spacing between the same kind of transistors of adjacent memory cells can also weaken the charge sharing, which leads to less MCU.