| Turbo译码器的改进算法及FPGA实现 |
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| 引用本文： | 于秀兰,冉静. Turbo译码器的改进算法及FPGA实现[J]. 计算机工程与应用, 2007, 43(3): 93-95 |
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| 作者姓名： | 于秀兰 冉静 |
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| 作者单位： | 重庆邮电学院,重庆,400065;北京大唐集团,北京,100038 |
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| 基金项目： | 重庆邮电学院青年创新基金 |
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| 摘 要： | 在传统的Turbo译码算法Log-MAP的基础上,对译码算法和SISO译码模块进行了优化,得到了改进的SW-Log-MAP算法,它在保证译码性能的前提下,大大降低了其运算复杂度,减少了存储空间。并且给出了改进译码算法硬件实现的设计方案,完成了Turbo译码器的FPGA实现,通过测试证明,译码器达到了设计要求。
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| 关 键 词： | Turbo码 迭代译码算法 改进的SW-Log-MAP算法 FPGA |
| 文章编号： | 1002-8331（2007）03-0093-03 |
| 修稿时间： | 2006-03-01 |
Improved decoding algorithm and FPGA-based implementation of Turbo coder |
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| YU Xiu-lan,RAN Jing. Improved decoding algorithm and FPGA-based implementation of Turbo coder[J]. Computer Engineering and Applications, 2007, 43(3): 93-95 |
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| Authors: | YU Xiu-lan RAN Jing |
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| Affiliation: | 1.Chongqing University of Posts and Telecommunications,Chongqing 400065,China ;2.Beijing Datang Mobile Communications Equipment Co. LTD.,Beijing 100038,China |
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| Abstract: | Derived from the conventional Log-MAP decoding algorithm of Turbo code and based on the decoding algorithm and the soft-input soft-output(SISO) decoding module,the improved SW-Log-MAP algorithm is put forward.Based on simulation,the conclusion is drawn that computational complexity and storage requirement are reduced with no performance degradation.Also,the FPGA-based design of the improved Turbo decoder and implementation of the decoder are finished,which meets the requirement of the design through testing. |
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| Keywords: | Turbo code iterative decoding algorithms the improved sliding-window Log-MAP algorithm Field Programmable Gate Array(FPGA) |
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