Hybrid Aging Delay Model Considering the PBTI and TDDB |
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| Authors: | Yong Miao Mao-Xiang Yi Gui-Mao Zhang Da-Wen Xu |
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| Affiliation: | 1.School of Electronic Science and Applied Physics,Hefei University of Technology,Hefei 230009,China |
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| Abstract: | With a 45 nm process technique, the shrinking silicon feature size brings in a high-k/metal gate which significantly exacerbates the positive bias temperature instability (PBTI) and time-dependent dielectric breakdown (TDDB) effects of a NMOS transistor. However, previous works presented delay models to characterize the PBTI or TDDB individually. This paper demonstrates that the delay caused by the joint effects of PBTI and TDDB widely differs from the cumulated result of the delay caused by the PBTI and TDDB, respectively, with the experiments on an inverter chain. This paper proposes a hybrid aging delay model comprising both the PBTI and TDDB effects by analyzing the relationship between the aging propagation delay and the inherent delay of the gate. Experimental results on the logic gates under 45 nm, 32 nm, 22 nm, and 16 nm CMOS technologies show that the maximum error between the proposed model and the actual value is less than 2.5%, meanwhile the average error is about 1.5%. |
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| Keywords: | Circuit aging positive bias temperature instability time-dependent dielectric breakdown |
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