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一种时序型总线硬件木马的植入与检测
引用本文:黄姣英,李胜玉,高成,杨达明. 一种时序型总线硬件木马的植入与检测[J]. 计算机工程, 2021, 47(3): 160-165. DOI: 10.19678/j.issn.1000-3428.0056353
作者姓名:黄姣英  李胜玉  高成  杨达明
作者单位:北京航空航天大学 可靠性与系统工程学院, 北京 100191
基金项目:"十三五"技术基础科研项目
摘    要:RS总线集成电路在航空航天及工业控制领域具有广泛的应用,随着集成电路硬件木马的检测成为研究热点,作为总线硬件木马研究领域的分支,其设计越来越受关注.在常规时序型硬件木马的基础上,针对RS232总线集成电路,设计一种基于可逆计数器的时序型总线硬件木马.采用Xillix公司的ISE软件在RTL层设计相应的RS232总线Ve...

关 键 词:RS232总线  硬件木马  寄存器传输级  Verilog代码  集成电路
收稿时间:2019-10-21
修稿时间:2020-02-20

Implantation and Detection of a Sequential Bus Hardware Trojan
HUANG Jiaoying,LI Shengyu,GAO Cheng,YANG Daming. Implantation and Detection of a Sequential Bus Hardware Trojan[J]. Computer Engineering, 2021, 47(3): 160-165. DOI: 10.19678/j.issn.1000-3428.0056353
Authors:HUANG Jiaoying  LI Shengyu  GAO Cheng  YANG Daming
Affiliation:School of Reliability and Systems Engineering, Beihang University, Beijing 100191, China
Abstract:RS bus integrated circuit has been widely used in aerospace and industrial control.With the hardware Trojan detection for integrated circuits becoming a research hotspot,as a branch of bus hardware Trojan research field,its design has been paid more and more attention.Based on conventional sequential hardware Trojans,this paper proposes a sequential bus hardware Trojan based on reversible counter for RS232 bus integrated circuits.The corresponding RS232 bus Verilog code is designed in the Register Transfer Level(RTL)layer by using ISE software of Xillix Company.Modelsim-based simulation and analysis are carried out in the case of trigger threshold of conventional and reversible hardware Trojans increasing by equal differences.The simulation results show that in the case of complex bus function requirements and large-scale data transmission,the reversible sequential Trojan has a lower trigger rate and flexibility and higher concealment than the conventional sequential hardware Trojan.
Keywords:RS232 bus  hardware Trojan  Register Transfer Level(RTL)  Verilog code  integrated circuit
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