| 并行高效BCH译码器设计及FPGA实现 |
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| 引用本文： | 张湘贤,杨涛,魏东梅,向玲. 并行高效BCH译码器设计及FPGA实现[J]. 计算机应用, 2012, 32(3): 867-869. DOI: 10.3724/SP.J.1087.2012.00867 |
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| 作者姓名： | 张湘贤 杨涛 魏东梅 向玲 |
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| 作者单位： | 西南科技大学 信息工程学院,四川 绵阳 621010 |
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| 基金项目： | 国防科工局核能开发科研项目，四川省科技计划项目 |
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| 摘 要： | 针对并行BCH译码器的特点,采用异或门实现有限域上常系数乘法,从而降低硬件复杂度。先计算部分错误位置多项式,再根据仿射多项式和格雷码理论,进行逻辑运算得到剩余的错误位置多项式,从而减少了系统所占用的资源。在现场可编程门阵列(FPGA)开发软件ISE10.1上进行了时序仿真,验证了该算法时间和空间的高效性。
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| 关 键 词： | 现场可编程门阵列 BCH译码器 仿射多项式 格雷码 |
| 收稿时间： | 2011-07-12 |
| 修稿时间： | 2011-11-22 |
Design and FPGA implementation of parallel high-efficiency BCH decoder |
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| ZHANG Xiang-xian , YANG Tao , WEI Dong-mei , XIANG Ling. Design and FPGA implementation of parallel high-efficiency BCH decoder[J]. Journal of Computer Applications, 2012, 32(3): 867-869. DOI: 10.3724/SP.J.1087.2012.00867 |
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| Authors: | ZHANG Xiang-xian YANG Tao WEI Dong-mei XIANG Ling |
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| Affiliation: | School of Information Engineering, Southwest University of Science and Technology, Mianyang Sichuan 621010, China |
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| Abstract: | According to the characteristics of parallel BCH decoder,the multiplication of constant coefficient in finite field was realized by using XOR gates to reduce hardware complexity.The part of the error location polynomial was calculated,and then the remaining error location polynomial could be obtained using the theory of affine polynomial and Gray code.The proposed algorithm reduces the system resources occupied.Through timing simulation on Field Programmable Gate Array(FPGA)’s development software ISE10.1,the high-efficiency of the algorithm on time and space has got verified. |
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| Keywords: | Field Programmable Gate Array(FPGA) BCH decoder affine polynomial Gray code |
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