| HEVC帧内预测Planar和DC模式的VLSI架构设计 |
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| 引用本文： | 刘新闯,蒋林,贺飞龙,田璞,周金娜. HEVC帧内预测Planar和DC模式的VLSI架构设计[J]. 计算机工程与应用, 2019, 55(17): 63-67. DOI: 10.3778/j.issn.1002-8331.1812-0041 |
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| 作者姓名： | 刘新闯 蒋林 贺飞龙 田璞 周金娜 |
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| 作者单位： | 西安邮电大学 电子工程学院,西安,710121;西安科技大学 集成电路实验室,西安,710054;西安邮电大学 计算机学院,西安,710121 |
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| 基金项目： | 国家自然科学基金;国家自然科学基金;国家自然科学基金;国家自然科学基金;陕西省科技统筹创新工程计划;陕西省重点研发计划 |
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| 摘 要： | 在对新一代高效视频编码(High Efficiency Video Coding,HEVC)帧内预测Planar和DC模式算法分析的基础上,分别提出了高效的超大规模集成电路(Very Large Scale Integration Circuit,VLSI)设计方案,旨在解决处理延时较长、资源占用较大的问题。针对Planar模式,提出一种在重组、合并算法的基础上,预测块复用的架构;针对DC模式,提出一种dcValue计算和滤波的基本块分离、各自复用不同块的架构。实验结果表明:所提架构与其他两种同类型架构相比,Planar模式实现平均处理延时减少了21%,资源消耗分别减少了14.7%和7%;DC模式实现平均处理延时减少了55%,同时资源消耗减少了22%和15%,能够满足1 920×1 080@30 f/s视频序列实时编码的需求。
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| 关 键 词： | 高效视频编码 帧内预测 Planar模式 DC模式 超大规模集成电路 |
VLSI Architecture Design of HEVC Intra Prediction Planar and DC Modes |
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| LIU Xinchuang,JIANG Lin,HE Feilong,TIAN Pu,ZHOU Jinna. VLSI Architecture Design of HEVC Intra Prediction Planar and DC Modes[J]. Computer Engineering and Applications, 2019, 55(17): 63-67. DOI: 10.3778/j.issn.1002-8331.1812-0041 |
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| Authors: | LIU Xinchuang JIANG Lin HE Feilong TIAN Pu ZHOU Jinna |
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| Affiliation: | 1.College of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’an 710121, China2.Laboratory of Integrated Circuit, Xi’an University of Science and Technology, Xi’an 710054, China3.College of Computer Science, Xi’an University of Posts and Telecommunications, Xi’an 710121, China |
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| Abstract: | Based on the analysis of the next-generation High Efficiency Video Coding（HEVC） intra prediction Planar and DC mode algorithms, a high-efficiency Very Large Scale Integration Circuit（VLSI） design scheme is proposed, for solving the problem of large resource occupation and long processing delay. Aiming at Planar mode, a framework for predicting block multiplexing based on recombination and merging algorithm is proposed. For DC mode, a basic block separation of dcValue calculation and filtering is proposed, and the architecture of different blocks is reused. The experimental results show that the proposed architecture reduces the average processing delay by 21% and the resource consumption by 14.7% and 7% respectively compared with the other two architectures of the same type. The average processing delay of the DC mode is reduced by 55%. At the same time, resource consumption is reduced by 22% and 15%, which can meet the real-time encoding requirements of 1 920×1 080@30 f/s video sequences. |
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| Keywords: | high efficiency video coding intra prediction Planar mode DC mode very large scale integration circuit |
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