Combined MMSE interference suppression and turbo coding for acoherent DS-CDMA system

The performance of a turbo-coded code division multiaccess system with a minimum mean-square error (MMSE) receiver for interference suppression is analyzed on a Rayleigh fading channel. In order to accurately estimate the performance of the turbo coding, two improvements are proposed on the conventional union bounds: the information of the minimum distance of a particular turbo interleaver is used to modify the average weight spectra, and the tangential bound is extended to the Rayleigh fading channel. Theoretical results are derived based on the optimum tap weights of the MMSE receiver and maximum-likelihood decoding. Simulation results incorporating iterative decoding, RLS adaptation, and the effects of finite interleaving are also presented. The results show that in the majority of the scenarios that we are concerned with, the MMSE receiver with a rate-1/2 turbo code will outperform a rate-1/4 turbo code. They also show that, for a bit error rate lower than 10^-3, the capacity of the system is increased by using turbo codes over convolutional codes, even with small block sizes     

A new high rate code scheme with highly parallel and low complexity decoding algorithm

A new high rate code scheme is proposed in this paper. It consists of serial concatenated recursive systematic ordinary (nonpunctured) convolutional codes with only 8 states in the trellis of the corresponding reciprocal dual codes. With a low complexity and highly parallel decoding algorithm, over additive white Gaussian noise channels, the proposed codes can achieve good bit error rate (BER) performance comparable to that of turbo codes and low density parity check (LDPC) codes. At code rate R=16/17, the overall decoding complexity of the proposed code scheme is almost half that of the LDPC codes.     

Soft-Decision Error Correction of NAND Flash Memory with a Turbo Product Code

As NAND flash memory fabrication technology scales down to 20 nm and below, the raw bit error rate increases very rapidly and conventional hard-decision based error correction does not provide enough protection. The turbo product code (TPC) based error correction with multi-precision output from NAND flash memory is promising because of high error-correcting performance and flexibility in code construction. In this work, we construct a rate-0.907 (36116, 32768) extended TPC for 2-bit MLC NAND flash memory, and apply the Chase–Pyndiah decoding algorithm. An efficient complexity reduction scheme is also proposed to eliminate redundant computations in the Chase–Pyndiah decoding algorithm. The replica parallel decoding is also employed to lower the error floor. The experimental results that include the effects of flash memory output precision are presented for a simulated flash memory channel.     

Zigzag codes and concatenated zigzag codes

This paper introduces a family of error-correcting codes called zigzag codes. A zigzag code is described by a highly structured zigzag graph. Due to the structural properties of the graph, very low-complexity soft-in/soft-out decoding rules can be implemented. We present a decoding rule, based on the Max-Log-APP (MLA) formulation, which requires a total of only 20 addition-equivalent operations per information bit, per iteration. Simulation of a rate-1/2 concatenated zigzag code with four constituent encoders with interleaver length 65 536, yields a bit error rate (BER) of 10^-5 at 0.9 dB and 1.3 dB away from the Shannon limit by optimal (APP) and low-cost suboptimal (MLA) decoders, respectively. A union bound analysis of the bit error probability of the zigzag code is presented. It is shown that the union bounds for these codes can be generated very efficiently. It is also illustrated that, for a fixed interleaver size, the concatenated code has increased code potential as the number of constituent encoders increases. Finally, the analysis shows that zigzag codes with four or more constituent encoders have lower error floors than comparable turbo codes with two constituent encoders     

Accumulate-Repeat-Accumulate Codes

In this paper, we propose an innovative channel coding scheme called accumulate-repeat-accumulate (ARA) codes. This class of codes can be viewed as serial turbo-like codes or as a subclass of low-density parity check (LDPC) codes, and they have a projected graph or protograph representation; this allows for high-speed iterative decoding implementation using belief propagation. An ARA code can be viewed as precoded repeat accumulate (RA) code with puncturing or as precoded irregular repeat accumulate (IRA) code, where simply an accumulator is chosen as the precoder. The amount of performance improvement due to the precoder will be called precoding gain. Using density evolution on their associated protographs, we find some rate-1/2 ARA codes, with a maximum variable node degree of 5 for which a minimum bit SNR as low as 0.08 dB from channel capacity threshold is achieved as the block size goes to infinity. Such a low threshold cannot be achieved by RA, IRA, or unstructured irregular LDPC codes with the same constraint on the maximum variable node degree. Furthermore, by puncturing the inner accumulator, we can construct families of higher rate ARA codes with thresholds that stay close to their respective channel capacity thresholds uniformly. Iterative decoding simulation results are provided and compared with turbo codes. In addition to iterative decoding analysis, we analyzed the performance of ARA codes with maximum-likelihood (ML) decoding. By obtaining the weight distribution of these codes and through existing tightest bounds we have shown that the ML SNR threshold of ARA codes also approaches very closely to that of random codes. These codes have better interleaving gain than turbo codes     

Turbo Receiver for Multicarrier Spread Spectrum Systems Employing Parity Bit Selected Spreading Sequences

In this paper a turbo receiver for multicarrier spread spectrum systems employing parity bit selected spreading code (MC-SS-PB) is proposed where detection and decoding are performed iteratively for each detected bit in the receiver. In MC-SS-PB systems, the parity bits generated by a linear block encoder are used to select a spreading code from a set of orthogonal spreading sequences. The selected spreading code is then used to spread the signals in all subcarriers. In the proposed receiver, soft information passes between the detector and the decoder on multiple iterations. Detection is performed by using the received signal in combination with the extrinsic likelihood provided by a soft input soft output decoder. The turbo receiver is further extended to a multiple user system where the multiple access interference is estimated in each iteration and subtracted out from the received signal. Simulations show a significant reduction in bit error rates when a turbo receiver is used in these systems.     

Extrinsic information in iterative decoding: a unified view

We address the use of the extrinsic information generated by each component decoder in an iterative decoding process. The BJCR algorithm proposed by Bahl et al. (1974) and the soft-output Viterbi algorithm (SOVA) are considered as component decoders. In both cases, we consider, in a unified view, various feedback schemes which use the extrinsic information in different fashions. Numerical results for a classical rate-1/2 turbo code and a serially concatenated code transmitted over a memoryless additive white Gaussian noise (AWGN) channel are provided. The performance of the considered schemes leads to interesting remarks about the nature of the extrinsic information     

Loosely coupled memory-based decoding architecture for low density parity check codes

Parallel decoding is required for low density parity check (LDPC) codes to achieve high decoding throughput, but it suffers from a large set of registers and complex interconnections due to randomly located 1's in the sparse parity check matrix. This paper proposes a new LDPC decoding architecture to reduce registers and alleviate complex interconnections. To reduce the number of messages to be exchanged among processing units (PUs), two data flows that can be loosely coupled are developed by allowing duplicated operations. In addition, intermediate values are grouped and stored into local storages each of which is accessed by only one PU. In order to save area, local storages are implemented using memories instead of registers. A partially parallel architecture is proposed to promote the memory usage and an efficient algorithm that schedules the processing order of the partially parallel architecture is also proposed to reduce the overall processing time by overlapping operations. To verify the proposed architecture, a 1024 bit rate-1/2 LDPC decoder is implemented using a 0.18-/spl mu/m CMOS process. The decoder runs correctly at the frequency of 200 MHz, which enables almost 1 Gbps decoding throughput. Since the proposed decoder occupies an area of 10.08 mm/sup 2/, it is less than one fifth of area compared to the previous architecture.     

Product accumulate codes: a class of codes with near-capacity performance and low decoding complexity

We propose a novel class of provably good codes which are a serial concatenation of a single-parity-check (SPC)-based product code, an interleaver, and a rate-1 recursive convolutional code. The proposed codes, termed product accumulate (PA) codes, are linear time encodable and linear time decodable. We show that the product code by itself does not have a positive threshold, but a PA code can provide arbitrarily low bit-error rate (BER) under both maximum-likelihood (ML) decoding and iterative decoding. Two message-passing decoding algorithms are proposed and it is shown that a particular update schedule for these message-passing algorithms is equivalent to conventional turbo decoding of the serial concatenated code, but with significantly lower complexity. Tight upper bounds on the ML performance using Divsalar's (1999) simple bound and thresholds under density evolution (DE) show that these codes are capable of performance within a few tenths of a decibel away from the Shannon limit. Simulation results confirm these claims and show that these codes provide performance similar to turbo codes but with significantly less decoding complexity and with a lower error floor. Hence, we propose PA codes as a class of prospective codes with good performance, low decoding complexity, regular structure, and flexible rate adaptivity for all rates above 1/2.     

A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check codedecoder

A 1024-b, rate-1/2, soft decision low-density parity-check (LDPC) code decoder has been implemented that matches the coding gain of equivalent turbo codes. The decoder features a parallel architecture that supports a maximum throughput of 1 Gb/s while performing 64 decoder iterations. The parallel architecture enables rapid convergence in the decoding algorithm to be translated into low decoder switching activity resulting in a power dissipation of only 690 mW from a 1.5-V supply     

Rate-1/2 component codes for nonbinary turbo codes

The iterative decoding structure and component maximum a posteriori decoders used for decoding binary concatenated codes can be extended to the nonbinary domain. This paper considers turbo codes over nonbinary rings, specifically ternary, quaternary, penternary, hexernary, and octernary codes. The best rate-1/2 component codes are determined using a practical search algorithm. The performance of the resulting rate-1/3 turbo codes on an additive white Gaussian noise channel using q-ary phase-shift keying modulation is given.     

Scalable image and video transmission using irregular repeat-accumulate codes with fast algorithm for optimal unequal error protection

This paper considers designing and applying punctured irregular repeat-accumulate (IRA) codes for scalable image and video transmission over binary symmetric channels. IRA codes of different rates are obtained by puncturing the parity bits of a mother IRA code, which uses a systematic encoder. One of the main ideas presented here is the design of the mother code such that the entire set of higher rate codes obtained by puncturing are good. To find a good unequal error protection for embedded bit streams, we employ the fast joint source-channel coding algorithm in Hamzaoui et al. to minimize the expected end-to-end distortion. We test with two scalable image coders (SPIHT and JPEG-2000) and two scalable video coders (3-D SPIHT and H.26L-based PFGS). Simulations show better results with IRA codes than those reported in Banister et al. with JPEG-2000 and turbo codes. The IRA codes proposed here also have lower decoding complexity than the turbo codes used by Banister et al.     

Analysis and design of punctured rate-1/2 turbo codes exhibiting low error floors

The objective of this paper is two-fold. Initially, we present an analytic technique to rapidly evaluate an approximation to the union bound on the bit error probability of turbo codes. This technique exploits the most significant terms of the union bound, which can be calculated straightforwardly by considering the properties of the constituent convolutional encoders. Subsequently, we use the bound approximation to demonstrate that specific punctured rate-1/2 turbo codes can achieve a lower error floor than that of their rate-1/3 parent codes. In particular, we propose pseudo-random puncturing as a means of improving the bandwidth efficiency of a turbo code and simultaneously lowering its error floor.     

Analysis of turbo codes with asymmetric modulation

If different energies are assigned to two outputs of a turbo encoder, the information bit and parity bit, then the performance will be changed according to the ratio of the information bit energy to the parity bit energy. The optimum point of the ratio may not be 1. As the rate of the turbo code is changed, the optimum point will also be changed. Rate 1/2, 1/3, 1/4 and 1/5 turbo codes with asymmetric modulation are considered     

Iterative reduced-search decoding for coded partial-response channels

The full-complexity soft-input/soft-output (SISO) detector based on the BCJR algorithm for coded partial-response channels has a computational complexity growing exponentially with channel memory length. In this letter, we propose a low complexity soft-output channel detector based on the Chase decoding algorithm, which was previously applied to decode turbo product codes. At each iteration, the proposed detector forms a candidate list using all possible combinations of bit patterns in the weakest indices based on tentative hard estimates and a priori information fed back from the outer decoder. To demonstrate the performance/complexity tradeoff of the proposed detector, simulation results over rate-8/9 turbo-coded EPR4 and ME/sup 2/PR4 channels are presented, respectively. It is shown that the proposed detector can significantly reduce the computational complexity with only a small performance loss compared to the BCJR algorithm.     

Improving the distance properties of turbo codes using a third component code: 3D turbo codes - [transactions letters]

Thanks to the probabilistic message passing performed between its component decoders, a turbo decoder is able to provide strong error correction close to the theoretical limit. However, the minimum Hamming distance (d_min) of a turbo code may not be sufficiently large to ensure large asymptotic gains at very low error rates (the so-called flattening effect). Increasing the d_min of a turbo code may involve using component encoders with a large number of states, devising more sophisticated internal permutations, or increasing the number of component encoders. This paper addresses the latter option and proposes a modified turbo code in which a fraction of the parity bits are encoded by a rate-1, third encoder. The result is a noticeably increased d_min, which improves turbo decoder performance at low error rates. Performance comparisons with turbo codes and serially concatenated convolutional codes are given.     

On the Performance and Implementation Issues of Interleaved Single Parity Check Turbo Product Codes

In this paper, both performance and complexity aspects of two-dimensional single parity check turbo product codes (I-SPC-TPC) are investigated. Based on the proposed I-SPC-TPC coding scheme, a parallel decoding structure is developed to increase the decoding throughput with minor performance degradation compared with the serial structure. For both decoding architectures, a new helical interleaver is constructed to further improve the coding gain. In terms of decoding algorithm, the extremely simple Sign-Min decoding is alternatively derived with only three additions needed to compute each bit's extrinsic information. For performance evaluation, (16, 14, 2)² single parity check turbo product code with code rate 0.766 over AWGN channel using QPSK modulation is considered. The simulation results using Sign-Min decoding show that it can achieve bit-error-rate of 10^?5 at signal-to-noise ratio of 3.8 dB with 8 iterations. Compared to the same rate and codeword length turbo product code composed of extended Hamming codes, the considered scheme can achieve similar performance with much less complexity. Important implementation issues such as the finite precision analysis, efficient sorting circuit design and interleaver memory management are also presented.     

光通信中基于分组Turbo码的一种改进Chase译码算法

为了适应光通信发展的要求,依据分组Turbo码(BTC)传统Chase译码算法的分析,提出了一种基于不对等可靠位数的改进新译码算法。使用该算法在每次迭代时将产生一个可靠度参数对外部信息进行修正,从而提高BTC的译码性能。仿真结果表明:在误码率(BER)为10-5且迭代4次的情况下,新BTC译码算法与传统Chase译码算法相比,其净编码增益(NCG)提高了0.9dB,并且在最差情况下给系统增加的译码复杂度都不大。     

Improved space-time codes using serial concatenation

In this letter, a new family of space-time codes is proposed. These codes employ a serially concatenated coding scheme with a standard space-time code as the outer code and a very simple rate-1 recursive code as the inner code. Adding this simple rate-1 recursive inner code does not decrease the bit rate and introduces only negligible complexity increase to the transmitter when compared to cases with standard space-time codes. An interleaver is embedded between the inner coder and the outer coder and the size of this interleaver determines the performance gain. We also provide a relatively low complexity iterative decoding procedure. For applications which can tolerate delay, significant gain can be achieved with the proposed approach     

Constrained systems with unconstrained positions

We develop methods for analyzing and constructing combined modulation/error-correcting codes (ECC codes), in particular codes that employ some form of reversed concatenation and whose ECC decoding scheme requires easy access to soft information (e.g., turbo codes, low-density parity-check (LDPC) codes or parity codes). We expand on earlier work of Wijngaarden and Immink (1998, 2001), Immink (1999) and Fan (1999), in which certain bit positions are reserved for ECC parity, in the sense that the bit values in these positions can be changed without violating the constraint. Earlier work has focused more on block codes for specific modulation constraints. While our treatment is completely general, we focus on finite-state codes for maximum transition run (MTR) constraints. We (1) obtain some improved constructions for MTR codes based on short block lengths, (2) specify an asymptotic lower bound for MTR constraints, which is tight in very special cases, for the maximal code rate achievable for an MTR code with a given density of unconstrained positions, and (3) show how to compute the capacity of the set of sequences that satisfy a completely arbitrary constraint with a specified set of bit positions unconstrained