Scalable FFT Processors and Pipelined Butterfly Units

This paper considers partial-column radix-2 FFT processors and realizations of butterfly operations. The area and power-efficiency of butterfly units to be used in the proposed processor organization based on bit-parallel multipliers, distributed arithmetic, and CORDIC are analyzed and compared. All the selected butterfly units are synthesized onto the same 0.11 μ ASIC technology allowing the results to be compared. The proposed processor organization permits the area of the FFT implementation to be traded against the computation time, thus the final structure can be easily tailored according to the requirements of the given application. The power consumption comparison shows that butterflies based on bit-parallel multipliers are power-efficient but have limitations on clock frequency. Butterflies based on distributed arithmetic could be used when higher clock frequencies are used. If extremely long FFTs are needed, the CORDIC based butterflies are applicable. Jarmo Takala received his M.Sc. (hons) degree in Electronics and Dr.Tech. degree in Information Technology from Tampere University of Technology, Tampere, Finland (TUT) in 1987 and 1999, respectively. From 1992 to 1996, he was a Research Scientist at VTT-Automation, Tampere, Finland. Between 1995 and 1996, he was a Senior Research Engineer at Nokia Research Center, Tampere, Finland. From 1996 to 1999, he was a Researcher at TUT. Currently, he is Professor in Computer Engineering at TUT and head of the Insitute of Digital and Computer Systems of TUT. His research interests include circuit techniques, parallel architectures, and design methodologies for digital signal processing systems. Konsta Punkka received his M.Sc. degree (hons) in Electrical Engineering from Tampere University of Technology (TUT), in 2002. He is currently working towards his Dr.Tech. degree as a research scientist in the Institute of Digital and Computer Systems at TUT. His research interests include optimization and implementation of DSP architectures.     

HIBI Communication Network for System-on-Chip

This paper presents a communication network targeted for complex system-on-chip (SoC) and network-on-chip (NoC) designs. The Heterogeneous IP Block Interconnection (HIBI) aims at maximum efficiency and minimum energy per transmitted bit combined with quality-of-service (QoS) in transfers. Other features include support for hierarchical topologies with several clock domains, flexible scalability, and runtime reconfiguration of network parameters. HIBI is intended for integrating coarse-grain components such as intellectual property (IP) blocks that have size of thousands of gates.HIBI has been implemented in VHDL and SystemC and synthesized on several CMOS technologies and on FPGA. A 32-bit wrapper requires 5400 gates and runs with 315 MHz on 0.18 μ m technology which shows that only minimal area overhead is paid for the advanced features. The area and frequency results are well comparable to other NoC proposals.Furthermore, data transfers are shown to approach the maximum theoretical performance for protocol efficiency. HIBI network is accompanied with a design framework with tools for optimizing the system through automated design space exploration. Erno Salminen Tampere University of Technology (TUT), Finland.Currently he is working towards his PhD degree in the Institute of Digital and Computer Systems (DCS) at TUT. His main research interests are digital systems design and communication issues in SoCs. Tero KangasTampere University of Technology (TUT), Finland.Since 1999 he has been working as a research scientist in the Institute of Digital and Computer Systems (DCS) at TUT. Currently he is working towards his PhD degree and his main research topics are system architectures and SoC design methodologies in multimedia applications. Timo D. H?m?al?ainen Tampere University of Technology (TUT), Finland. He was nominated to full professor at TUT/Institute of Digital and Computer Systems in 2001. He heads the DACI research group that focuses on three main research areas: wireless sensor networks, high-performance multi-DSP and hardware based video encoding, and design flow tools for heterogeneous MP-SoC platforms. Jouni Riihi?mki Tampere University of Technology (TUT), Finland. Currently he is working as a senior design engineer at Nokia Technlogy Platforms. He is also working towards his PhD degree. His research interests include SoC design and verification methodologies. Vesa Lahtinen received his M.Sc. and Ph.D. from TUT in 1998 and 2004, respectively. In TUT, his main research areas were system-on-chips and their interconnects. Currently, Dr. Lahtinen is a Senior Research Engineer in the Computing Architectures Laboratory of Nokia Research Center (NRC) concentrating on architecture modeling and, specifically, memory architectures. Kimmo Kuusilinna Tampere University of Technology (TUT), Finland. His main research interests include system-level design and verification, on-chip interconnections, and parallel memories. Currently he is working as a senior research engineer at the Nokia Research Center.     

Methodology for Refinement and Optimisation of Dynamic Memory Management for Embedded Systems in Multimedia Applications

In multimedia applications, run-time memory management support has to allow real-time memory de/allocation, retrieving and processing of data. Thus, its implementation must be designed to combine high speed, low power, large data storage capacity and a high memory bandwidth. In this paper, we assess the performance of our new system-level exploration methodology to optimise the memory management of typical multimedia applications in an extensively used 3D reconstruction image system [1, 2]. This methodology is based on an analysis of the number of memory accesses, normalised memory footprint¹ and energy estimations for the system studied. This results in an improvement of normalised memory footprint up to 44.2% and the estimated energy dissipation up to 22.6% over conventional static memory implementations in an optimised version of the driver application. Finally, our final version is able to scale perfectly the memory consumed in the system for a wide range of input parameters whereas the statically optimised version is unable to do this.The original version of this paper first appeared in the Proceedings of Signal Processing Systems 2003.Marc Leeman has as professional research interests hardware/software co-design, code optimisation in general and optimisation of dynamic data types and dynamic memory management for low power embedded systems in particular. Personal interests include Open and Free software development, software configuration and GNU/Debian package maintenance. He received an engineering degree, a master in artificial intelligence and a Ph.D. in electrical engineering in 1997, 1998 and 2004 respectively, all at the K.U. Leuven. He is a member of the IEEE Computer Society. Currently, he works as an R&D Engineer for Barco Control-rooms Division (BCD) on hardware/software co-design for streaming video products.David Atienza received the M.Sc. degree in Computer Sciences from the Complutense University of Madrid (UCM), Spain in 2001. Since then he has joined the Department of Computer Architecture and Automation of Complutense University of Madrid as a sandwich Ph.D. student half-time at the Inter-university Micro-Electronics Centre (IMEC), Heverlee, Belgium. His research interests include optimisation of dynamic memory management on multimedia and wireless network applications for low power and high performance embedded systems, computer architecture and high-level design automation.Geert Deconinck is Associate Professor (hoofddocent) at the K.U. Leuven (Belgium) since 2003 and staff member of the research group ELECTA (Electrical Energy and Computing Architectures). His research interests include the design and assessment of software-based solutions to meet dependability, real-time, and cost constraints for embedded systems. In this field, he has authored and co-authored more than 120 publications in international journals and conference proceedings. He received his M.Sc. in Electrical Engineering and his Ph.D. in Applied Sciences from the K.U. Leuven, Belgium in 1991 and 1996 respectively. He was a visiting professor (bijzonder gastdocent) at the K.U. Leuven in 1999–2003. - Flanders (Belgium) in the period 1997–2003.Vincenzo De Florio received his MSc degree in computer science in 1987 and his PhD degree in engineering in 2000, respectively from the University of Bari, Italy, and the University of Leuven, Belgium. He is currently post-doctoral researcher at the University of Antwerp, where he is doing research on adaptive and dependable mobile applications. Previously he had been researcher and lecturer with Tecnopolis/SASIAM (ECMI School for Advanced Studies in Industrial and Applied Mathematics) and member of Tecnopolis/Robotic lab, where he was responsible for design of parallel robotic vision applications. Currently he is also a reviewer for several conferences and for the Journal of System Architectures.José M. Mendías received the M.Sc. and Ph.D. degrees in physics from the Complutense University of Madrid in 1992 and 1998, respectively. He joined the Department of Computer Architecture and Systems Engineering, Complutense University in 1992 as a lecturer, and became an associate professor in 2001. Since 2002, he is Vice-dean of the Computer Science Faculty at the same University. His current research interests include design automation, computer architecture and formal methods.Chantal Ykman-Couvreur is born in 1956. She received the mathematics degree from the Facultes Universitaires Notre-Dame de la Paix of Namur in 1979. She first worked at PHILIPS Research Laboratory of Belgium, from 1979 until 1991. Her main activities were concentrated on information theory and coding, cryptography and multi-level logic synthesis for VLSI circuits. Then, she joined IMEC, where she was responsible at IMEC for the dynamic memory management and the system-level design flow in the Matisse compiler for network protocol components (ATM, Internet Protocol, etc). Currently, she works on the task concurrency management design flow in the Matador project.Francky Catthoor received the engineering degree and a Ph.D. in electrical engineering from the Katholieke Universiteit Leuven, Belgium in 1982 and 1987 respectively. Since 1987, he has headed several research domains in the area of high-level and system synthesis techniques and architectural methodologies, all within the Design Technology for Integrated Information and Telecom Systems (DESICS—formerly VSDM) division at the Inter-university Micro-Electronics Centre (IMEC), Heverlee, Belgium. Currently he is an IMEC fellow. He is part-time full professor at the EE department of the K.U. Leuven.In 1986 he received the Young Scientist Award from the Marconi International Fellowship Council. He has been associate editor for several IEEE and ACM journals, like Transactions on VLSI Signal Processing, Transactions on Multi-media, and ACM TODAES. He was the program chair of several conferences including ISSS97 and SIPS01.Rudy Lauwereins is vice-president of IMEC, Belgiums Interuniversity Micro-Electronic Centre, which performs research and development, ahead of industrial needs by 3 to 10 years, in microelectronics, nano-technology, enabling design methods and technologies for ICT systems. He leads the DESICS division of 185 researchers, currently focused on the development of re-configurable architectures, design methods and tools for wireless and multimedia applications. He is also a part-time Professor at the Katholieke Universiteit Leuven, Belgium. He had obtained a Ph.D. in Electrical Engineering in 1989. Rudy Lauwereins served in numerous international program committees and organisational committees, and gave many invited and keynote speeches. He is vice-chair of the board of DSP Valley and member of the board of several spin-off companies. He is a senior member of the IEEE.     

A Broadband Quadrature-Modulator with Integrated Baluns

A broadband direct-conversion quadrature-modulator has been implemented in 0.8 m SiGe with integrated baluns in its RF-signal paths. Measured performance includes IRR-values at better than –40 dBc in 0.75–3.6 GHz with output power levels in excess of –20 dBm. For this performance circuit draws 46 mA from a single 2.5 V supply.Esa Tiiliharju was born in Rovaniemi, Finland, in 1966. He received the M.Sc. degree in Information Technology in 1995, and the Lic.Tech degree in electrical engineering in 1998, both from Helsinki University of Technology, Finland.From 1996 to July 1997 he was employed as assistant at Helsinki University of Technology. He has been holding a position of a research assistant from 1997, and he is currently working towards the Ph.D. degree in the Electronic Circuit Design Laboratory at Helsinki University of Technology.His research interests include the design of integrated low-power circuits for portable telecommunication applications. He has designed and measured several integrated circuits for this application area. He is author or co-author for several international refereed conference and journal publications on analog integrated circuits.Kari A.I. Halonen was born in Helsinki, Finland, on May 23, 1958. He received the M.Sc. degree in electrical engineering from the Helsinki University of Technology (HUT) in 1982 and the Ph.D. degree in electrical engineering from the Katholieke Universiteit Leuven, Heverlee, Belgium, in 1987.From 1982 to 1984, he was with HUT as an Assistant and with the Technical Research Center of Finland as a Research Assistant. From 1984 to 1987, he was a Research Assistant with the E.S.A.T. Laboratory, Katholieke Universiteit Leuven, with a temporary grant from the Academy of Finland. Since 1988, he has been with the Electronic Circuit Design Laboratory, HUT, as a Senior Assistant from 1988 to 1990, and as the Director of the Integrated Circuit Design Unit of the Microelectronics Center from 1990 to 1993. He was on leave of absence during the academic year 1992–1993, acting as Research and Development Manager with Fincitec Inc., Finland. From 1993 to 1996, he was an Associate Professor, and since 1997, he has been a full Professor with the Faculty of Electrical Engineering and Telecommunications, HUT. He became the Head of Electronic Circuit Design Laboratory year 1998. He was the Technical Program Committee Chairman for the European Solid-State Circuits Conference in 2000. He is the author or coauthor of over 150 international and national conference and journal publications on analog integrated circuits, and holds several patents on analog integrated circuits. His research interests are in CMOS and BiCMOS analog integrated circuits, particularly for telecommunication applications.Dr. Halonen was an Associate Editor of the IEEE Transactions on Circuits and Systems–Part I: Fundamental Theory and Applications from 1997 to 1999. He has been a Guest Editor for the IEEE Journal of Solid-State Circuits. He received the BeatriceWinner Award from the IEEE International Solid-State Circuits Conference in 2002.     

Scalable Architecture for SoC Video Encoders

Evolving video coding standards demand functional flexibility for implementations, not only at design time but also after fabrication. This paper presents a System-on-Chip design approach with a feasible combination of performance, scalability, programmability, area efficiency, and design time effort for a video encoder. The encoder is based on a homogeneous master-slave processor architecture. Each slave encodes a part of the frame in the Single Program Multiple Data (SPMD) data parallel model. Both shared and distributed memory architectures are presented. Design effort is reduced by identical program codes, automated assembly of software and hardware modules independent of the number and type of processors, as well as our flexible on-chip communication network called Heterogeneous IP Block Interconnection (HIBI). A case study implementation with two to ten simple ARM7 processors, 32-bit HIBI bus and non-optimized processor-independent software gives the performance from 6 to 53 fps for QCIF. The whole encoder area ranges from 173 to 770 kgates excluding the memories. The relation scales reasonably well to systems with more powerful processors and optimized code. The optimization of the communication network shows that with more than six slaves even a serial HIBI connection with 100 MHz speed is feasible. HIBI and the parallelization approach allow exploration and optimization of the communication both at the application and architecture layers. Tero Kangas, MSc ’01, Tampere University of Technology (TUT). Since 1999 he has been working as a research scientist in the Institute of Digital and Computer Systems (DCS) at TUT. Currently he is working towards his PhD degree and his main research topics are system architectures and SoC design methodologies in multimedia applications. Kimmo Kuusilinna, PhD ’01, TUT. His main research interests include system-level design and verification, interconnection networks, and parallel memories. Currently he is working as a senior research engineer at the Nokia Research Center. Timo D. H?m?l?inen, MSc ’93, PhD ’97, TUT. He acted as a senior research scientist and project manager at TUT in 1997-2001. He was nominated to full professor at TUT/Institute of Digital and Computer Systems in 2001. He heads the DACI research group that focuses on three main lines: wireless local area networking and wireless sensor networks, high-performance DSP/HW based video encoding, and interconnection networks with design flow tools for heterogeneous SoC platforms.     

Signaled Step Size for Downlink Power Control of Dedicated Channels in UTRA TDD

This paper discusses downlink inner loop power control of dedicated channels in UTRA TDD. The current UTRA TDD downlink power control is similar to one in UTRA FDD mode, that comprises of closed inner loop and quality based outer loop. However, due to the time division feature and associated fexibility with asymmetry of TDD, the inner loop can not react as fast as in FDD and it is affected by rapid changes in environment. Therefore, the effect of the inner loop algorithm to the performance of UTRA TDD network is studied in this paper. Especially, the use of asymmetric step sizes for power up and power down commands is evaluated in contrast to the conventional symmetric power adjustment. Since it would be beneficial for the downlink inner loop power control to reach the target SIR as fast as possible, the power control step size based on the difference between the UE measured SIR and target SIR would be the most desirable power adjustment. Since the effectiveness of this type of an algorithm depends on available signaling bandwidth that is used, a study is carried out to find the tradeoff between the signaling bandwidth and related network performance.Janne Kurjenniemi was born in Jyväskylä, Finland, in March 1974. He received the M.Sc. in telecommunications in 2001 from the University of Jyväskylä, Jyväskyl, Finland. He is working as a Researcher at the Department of Mathematical Information Technology, University of Jyväskylä. His research interests include radio resource management for wireless communication systems.Otto-Aleksanteri Lehtinen was born in Tampere, Finland, in September 1971. He received the Master of Science in Technology in 1999 from the Helsinki University of Technology, Department of Electrical engineering (major in radio technology, minor signal processing and computer devices). His research interests include radio resource management for wireless communication systems.Tapani Ristaniemi was born in Kauhava, Finland, in 1971. He received the M.Sc. in mathematics in 1995, Ph.Lic. in applied mathematics in 1997, and Ph.D. in telecommunications in 2000 from the University of Jyväskylä, Jyväskylä, Finland. During 2001–2003 he was a professor of telecommunications at the Department of Mathematical Information Technology, University of Jyväskylä. In 2003 he joined the Institute of Communications Engineering in the Tampere University of Technology, Finland, where he has been a professor of wireless data communications. His research interests include signal processing for communications and radio resource management for wireless networks.     

Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test

This paper presents the results of resistive-open defect insertion in different locations of Infineon 0.13 m embedded-SRAM with the main purpose of verifying the presence of dynamic faults. This study is based on the injection of resistive defects as their presence in VDSM technologies is more and more frequent. Electrical simulations have been performed to evaluate the effects of those defects in terms of detected functional faults. Read destructive, deceptive read destructive and dynamic read destructive faults have been reproduced and accurately characterized. The dependence of the fault detection has been put in relation with memory operating conditions, resistance value and clock cycle, and the importance of at speed testing for dynamic fault models has been pointed out. Finally resistive Address Decoder Open Faults (ADOF) have been simulated and the conditions that maximize the fault detection have been discussed as well as the resulting implications for memory test.This work has been partially funded by the French government under the framework of the MEDEA + A503 ASSOCIATE European program.A paper based on this work was presented at the Eighth IEEE European Test Workshop, Maastricht, The Netherlands, May 2003.Simone Borri received the M.Sc. Degree (summa cum laude) in Electronics Engineering from the University of Pisa (Italy) in 1995. In 1997 he joined STMicroelectronics as a digital designer in the DSP development group of S.S.D. (formerly Parthus, now Ceva), Dublin, Ireland. From 1998 to 2000 he was with ST Microelectronics, Milan, Italy as ASIC DSP designer in the Car Communication business unit. Since 2000 he is with Infineon Technologies, Sophia-Antipolis, France as Staff design engineer in the embedded-SRAM design group. He has recently joined the Secure Mobile System Business Unit. His current interests include BIST, DFT techniques and SoC verification. Simone is an IEEE member since 1995.Magali Hage-Hassan was born near Lyon (France) in 1979. She received a Master of Science degree of Microelectronics and Automatics from the Institute of Engineering Sciences of Montpellier in 2003. She is currently working for Infineon in the memory library department in Sophia-Antipolis. She participated to the European research project MEDEA associate. Hage-Hassans interest include memory test.Luigi Dilillo was born in Barletta (Italy) in 1974. At this moment he is doing his last year of Ph.D. in the Microelectronics Department of the Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM) in France. He received his degree in Electrical Engineering in 2001, at Politecnico di Torino (Italy). His researches include MEMS and digital circuits. At this moment he is working on delay-fault testing, and memory testing.Patrick Girard is presently Researcher at CNRS (French National Center for Scientific Research), and works in the Microelectronics Department of the LIRMM (Laboratory of Informatics, Robotics and Microelectronics of Montpellier—France). His research interests include the various aspects of digital testing, with special emphasis on DfT, logic BIST, delay fault testing and diagnosis, low power testing and memory testing. He has authored and co-authored 1 book and more than 100 papers on these fields. He has managed several European research projects and industrial research contracts. He is Editor-in-Chief of JOLPE—Journal of Low Power Electronics, and Associate Editor of JEC—Journal of Embedded Computing. He will serve as Program vice-Chair for the International Conference on Embedded And Ubiquitous Computing in 2005 and as Program Chair for the IEEE International Workshop on Electronic Design, Test & Applications in 2006. He is also topic chair of two European conferences (DATE and ETS) and is member of the program committee of several other international conferences. Patrick GIRARD obtained the Ph.D. degree in microelectronics from the University of Montpellier in 1992 and the Habilitation à Diriger des Recherches degree from the University of Montpellier in 2003.Serge Pravossoudovitch was born in 1957. He is currently professor in the electrical and computer engineering department of the University of Montpellier and his research activities are performed at LIRMM (Laboratoire dInformatique, de Robotique et de Microélectronique de Montpellier). He got the Ph.D. degree in electrical engineering in 1983 for his work on symbolic layout for IC design. Since 1984, he is working in the testing domain. He obtained the doctorat détat degree in 1987 for his work on switch level automatic test pattern generation. He is presently interested in memory testing, delay fault testing, design for testability and power consumption optimization. He has authored and co-authored numerous papers on these fields, and has supervised several Ph.D. dissertations. He has also participated to several European projects (Microelectronic regulation, Esprit, Medea).Arnaud Virazel was born in Montpellier (France) in 1974. He is presently assistant professor at the university of Montpellier, and works with the LIRMM (Laboratoire dInformatique, de Robotique et de Microélectronique de Montpellier). He received the B.Sc. (1995) and the M.Sc. (1997) degrees in Electrical Engineering and the Ph.D. (2001) degree in Microelectronics, all from the University of Montpellier/LIRMM. A. Virazels interests include delay testing, memory testing and power optimization during test.     

Strongly Consistent Access Algorithms for Wireless Data Networks

In wireless data networks such as the WAP systems, the cached data may be time-sensitive and strong consistency must be maintained (i.e., the data presented to the user at the WAP handset must be the same as that in the origin server). In this paper, we study the cached data access algorithms in such systems. Two caching algorithms are investigated. In Algorithm I, Pull-Each-Read, whenever a data access occurs, the client always asks the server whether the cached entry in the client is valid or not. In Algorithm II, Callback, the server always invalidates the cached entry in the client whenever an update occurs. Analytic models are proposed to evaluate the performance of these algorithms. Our studies show that Algorithm II outperforms Algorithm I if the data access rate is high and the access pattern is irregular. We also design an adaptive mechanism to effectively switch between the two algorithms to take advantages of both algorithms. We also apply the single-level cached data access algorithms for the multi-level cache hierarchy. Our study indicates that with appropriate arrangement, strongly consistent cached data access for wireless Internet (such as WAP) can be efficiently supported.Yuguang Fang received the B.S. and M.S. degrees in Mathematics from Qufu Normal University, Qufu, Shandong, China, in 1984 and 1987, respectively, a Ph.D degree from Department of Systems, Control and Industrial Engineering at Case Western Reserve University, Cleveland, Ohio, in January 1994, and a Ph.D degree from Department of Electrical and Computer Engineering at Boston University, Massachusetts, in May 1997.From 1987 to 1988, he held research and teaching positions in both Department of Mathematics and the Institute of Automation at Qufu Normal University. He held a post-doctoral position in Department of Electrical and Computer Engineering at Boston University from June 1994 to August 1995. From June 1997 to July 1998, he was a Visiting Assistant Professor in Department of Electrical Engineering at the University of Texas at Dallas. From July 1998 to May 2000, he was an Assistant Professor in the Department of Electrical and Computer Engineering at New Jersey Institute of Technology, Newark, New Jersey. From May 2000 to July 2003, he was an Assistant Professor in the Department of Electrical and Computer Engineering at University of Florida, Gainesville, Florida, where he has been an Associate Professor since August 2003. His research interests span many areas including wireless networks, mobile computing, mobile communications, automatic control, and neural networks. He has published over ninety papers in refereed professional journals and conferences. He received the National Science Foundation Faculty Early Career Development Award in 2001 and the Office of Naval Research Young Investigator Award in 2002. He is listed in Marquis Whos Who in Science and Engineering, Whos Who in America and Whos Who in World.Dr. Fang has actively engaged in many professional activities. He is a senior member of the IEEE and a member of the ACM. He is an Editor for IEEE Transactions on Communications, an Editor for IEEE Transactions on Wireless Communications, an Editor for ACM Wireless Networks, an Area Editor for ACM Mobile Computing and Communications Review, an Associate Editor for Wiley International Journal on Wireless Communications and Mobile Computing, and an Editor for IEEE Wireless Communications. He was an Editor for IEEE Journal on Selected Areas in Communications: Wireless Communications Series and the feature editor for Scanning the Literature in IEEE Wireless Communications (formerly IEEE Personal Communications). He has also actively involved with many professional conferences such as ACM MobiCom02, ACM MobiCom01, IEEE INFOCOM04, INFOCOM03, INFOCOM00, INFOCOM98, IEEE WCNC02, WCNC00 (Technical Program Vice-Chair), WCNC99, and International Conference on Computer Communications and Networking (IC3N98) (Technical Program Vice-Chair).Yi-Bing Lin received his BSEE degree from National Cheng Kung University in 1983, and his Ph.D. degree in Computer Science from the University of Washington in 1990. From 1990 to 1995, he was with the Applied Research Area at Bell Communications Research (Bellcore), Morristown, NJ. In 1995, he was appointed as a professor of Department of Computer Science and Information Engineering (CSIE), National Chiao Tung University (NCTU). In 1996, he was appointed as Deputy Director of Microelectronics and Information Systems Research Center, NCTU. During 1997-1999, he was elected as Chairman of CSIE, NCTU. His current research interests include design and analysis of personal communications services network, mobile computing, distributed simulation, and performance modeling. Dr. Lin has published over 150 journal articles and more than 200 conference papers.Dr. Lin is a senior technical editor of IEEE Network, an editor of IEEE Trans. on Wireless Communications, an associate editor of IEEE Trans. on Vehicular Technology, an associate editor of IEEE Communications Survey and Tutorials, an editor of IEEE Personal Communications Magazine, an editor of Computer Networks, an area editor of ACM Mobile Computing and Communication Review, a columnist of ACM Simulation Digest, an editor of International Journal of Communications Systems, an editor of ACM/Baltzer Wireless Networks, an editor of Computer Simulation Modeling and Analysis, an editor of Journal of Information Science and Engineering, Program Chair for the 8th Workshop on Distributed and Parallel Simulation, General Chair for the 9th Workshop on Distributed and Parallel Simulation. Program Chair for the 2nd International Mobile Computing Conference, Guest Editor for the ACM/Baltzer MONET special issue on Personal Communications, a Guest Editor for IEEE Transactions on Computers special issue on Mobile Computing, a Guest Editor for IEEE Transactions on Computers special issue on Wireless Internet, and a Guest Editor for IEEE Communications Magazine special issue on Active, Programmable, and Mobile Code Networking. Lin is the author of the book Wireless and Mobile Network Architecture (co-author with Imrich Chlamtac; published by John Wiley & Sons). Lin received 1998, 2000 and 2002 Outstanding Research Awards from National Science Council, ROC, and 1998 Outstanding Youth Electrical Engineer Award from CIEE, ROC. He also received the NCTU Outstanding Teaching Award in 2002. Lin is an Adjunct Research Fellow of Academia Sinica, and is Chair Professor of Providence University. Lin serves as consultant of many telecommunications companies including FarEasTone and Chung Hwa Telecom. Lin is an IEEE Fellow.     

A 200 MHz 4.8 mW 3 V Fully Differential CMOS Sample-and-Hold Circuit with Low Hold Pedestal

Wide frequency bandwidth has been internationally allocated for unlicensed operation around the oxygen absorption frequency at 60 GHz. A power amplifier and a low noise amplifier are presented as building blocks for a T/R-unit at this frequency. The fabrication technology was a commercially available 0.15 m gallium arsenide (GaAs) process featuring pseudomorphic high electron mobility transistors (PHEMT). Using on-wafer tests, we measured a gain of 13.4 dB and a +17 dBm output compression point for the power amplifier at 60 GHz centre frequency when the MMIC was biased to 3 volts V_dd. At the same frequency, the low noise amplifier exhibited 24 dB of gain with a 3.5 dB noise figure. The AM/AM and AM/PM characteristics of the power amplifier chip were obtained from the large-signal S-parameter measurement data. Furthermore, the power amplifier was assembled in a split block package, which had a WR-15 waveguide interface in input and output. The measured results show a 12.5 dB small-signal gain and better than 8 dB return losses in input and output for the packaged power amplifier.Mikko Kärkkäinen received the M.Sc. degree in electrical engineering from the Helsinki University of Technology, Espoo, Finland, in 2000, and is currently working toward the Ph.D. degree at the Electronic Circuit Design Laboratory, Helsinki University of Technology. He is interested in millimetre wave circuit design.Mikko Varonen received the M.Sc. degree in electrical engineering from the Helsinki University of Technology, Espoo, Finland, in 2002. He is currently working toward the Ph.D. degree in electrical engineering at the Electronic Circuit Design Laboratory, Helsinki University of Technology. His research interests involve millimetre-wave integrated circuits.Pekka Kangaslahti received the M.Sc. and Ph.D. degrees in electrical engineering from the Helsinki University of Technology, Finland, in 1992 and 1999, respectively. Since 1999 he has been a visiting scientist at the NASA Jet Propulsion Laboratory, Pasadena, USA. His research interests include nonlinear microwave and millimetre wave monolithic circuits, especially for signal generation in telecommunication and radar applications.Kari A. I. Halonen was born in Helsinki, Finland, on May 23, 1958. He received the M.Sc. degree in electrical engineering from Helsinki University of Technology, Finland, in 1982, and the Ph.D. degree in electrical engineering from the Katholieke Universiteit Leuven, in Heverlee, Belgium, in 1987.From 1982 to 1984 he was employed as assistant at Helsinki University of Technology and as research assistant at the Technical Research Center of Finland. From 1984 to 1987 he was a research assistant at the E.S.A.T. Laboratory of the Katholieke Universiteit Leuven, enjoying also a temporary grant of the Academy of Finland. Since 1988 he has been with the Electronic Circuit Design Laboratory, Helsinki University of Technology, as senior assistant (1988–1990), and the director of the Integrated Circuit Design Unit of the Microelectronics Center (1990–1993). He was on leave of absence the academic year 1992–93, acting as R&D manager in Fincitec Inc., Finland. From 1993 to 1996 he has been an associate professor, and since 1997 a full professor at the Faculty of Electrical Engineering and Telecommunications, Helsinki University of Technology. He became the Head of Electronic Circuit Design Laboratory year 1998. From 1997 to 1999 he was an associate editor of IEEE Transactions on Circuits and Systems I. He has been a guest editor for IEEE Journal of Solid-State Circuits and the Technical Program Committee Chairman for European Solid-State Circuits Conference year 2000. He has been awarded the Beatrice Winner Award in ISSCC02 Conference year 2002.     

A Broadband Quadrature-Modulator in Standard 0.13 μm CMOS

A polyphase filtering topology is proposed which uses parallel switchable RC-networks for accurate broadband 90^∘ phasing. A 0.13μm CMOS prototype using the quadrature-generation network in a direct-conversion quadrature-modulator achieves a measured image-rejection ratio of −39 dBc or better in 0.6–2.5 GHz while consuming only 66 mW from a 2.2 V single supply. Esa Tiiliharjuwas born in Rovaniemi, Finland, in 1966. He received the M.Sc. degree in Information Technology in 1995, and the Lic.Tech degree in electrical engineering in 1998, both from Helsinki University of Technology, Finland. From 1996 to July 1997 he was employed as an assistant at Helsinki University of Technology. He has held a position as a research assistant since 1997, and he is currently working towards his Ph.D. degree in the Electronic Circuit Design Laboratory at Helsinki University of Technology. His research interests include the design of integrated low-power circuits for portable telecommunication applications. He has designed and measured several integrated circuits for this application area. He is the author or co-author of several internationally-refereed conference and journal publications on analog integrated circuits. Kari A.I. Halonenwas born in Helsinki, Finland, on May 23, 1958. He received the M.Sc. degree in electrical engineering from the Helsinki University of Technology (HUT) in 1982 and the Ph.D. degree in electrical engineering from the Katholieke Universiteit Leuven, Heverlee, Belgium, in 1987. From 1982 to 1984, he was with HUT as an Assistant and with the Technical Research Center of Finland as a Research Assistant. From 1984 to 1987, he was a Research Assistant with the E.S.A.T. Laboratory, Katholieke Universiteit Leuven, with a temporary grant from the Academy of Finland. Since 1988, he has been with the Electronic Circuit Design Laboratory, HUT, as a Senior Assistant from 1988 to 1990, and as the Director of the Integrated Circuit Design Unit of the Microelectronics Center from 1990 to 1993. He was on leave of absence during the academic year 1992–1993, acting as Research and Development Manager with Fincitec Inc., Finland. From 1993 to 1996, he was an Associate Professor, and since 1997, he has been a full Professor with the Faculty of Electrical Engineering and Telecommunications, HUT. He became the Head of Electronic Circuit Design Laboratory year 1998. He was the Technical Program Committee Chairman for the European Solid-State Circuits Conference in 2000. He is the author or coauthor of over 150 international and national conference and journal publications on analog integrated circuits, and holds several patents on analog integrated circuits. His research interests are in CMOS and BiCMOS analog integrated circuits, particularly for telecommunication applications. Dr. Halonen was an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–PART I: FUNDAMENTAL THEORY AND APPLICATIONS from 1997 to 1999. He has been a Guest Editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS. He received the BeatriceWinner Award from the IEEE International Solid-State Circuits Conference in 2002.[c-halonen.eps]     

Implementation of a Wireless Multimedia DSP Chip for Mobile Applications

This paper presents the implementation of a wireless multimedia DSP chip for mobile applications. The implemented DSP chip supports communication instructions for Viterbi, timing synchronization, etc. as well as multimedia instructions. The DSP can handle variable length data and perform four MACs in a cycle. The proposed DSP employs parallel processing techniques, such as SIMD, vector processing, DSP schemes and adopts low power features for wireless applications. The implemented DSP chip includes test circuits and various peripherals, such as DMA, bus arbitration, timer, etc. This chip has been modeled by Verilog HDL and implemented using the 0.35 m HCB60 library. The total gate count excluding memory is about 170,000 gates and the clock frequency is 100 MHz.Junghoo Lee received the B.S. degree in electronic engineering from Ajou University, Suwon, Korea in 2002. He is currently working toward the Ph.D. degree with School of Electrical and Computer Engineering, Ajou University. His main research interests include SOC design and application-specific DSP chip design.Myung H. Sunwoo received the B.S. degree in electronic engineering from the Sogang University in 1980, the M.S. degree in electrical and electronics from the Korea Advanced Institute of Science and Technology in 1982, and the Ph.D. degree in electrical and computer engineering from the University of Texas at Austin in 1990.He worked for Electronics and Telecommunications Research Institute (ETRI) in Daejeon, Korea from 1982 to 1985 and Digital Signal Processor Operations, Motorola, Austin, TX from 1990 to 1992. Since 1992, he has been a Professor with the School of Electrical and Computer Engineering, Ajou University in Suwon, Korea. In 2000, he was a Visiting Professor in the Department of Electrical and Computer Engineering, the University of California, Davis, CA. He is the Director of the National Research Laboratory sponsored by the Ministry of Science and Technology. His research interests include VLSI architectures, SOC design for multimedia and communications, and application-specific DSP architectures.Dr. Sunwoo has published more than 120 papers in international transactions/journals and conferences and also has 28 patents including five U.S. patents. He served as a Technical Program Chair of the IEEE Workshop on Signal Processing Systems (SIPS) in 2003 and a member of the technical program committee of various international conferences. He has received a number of research awards from the Ministry of Commerce, Industry and Energy, Samsung Electronics, and professional foundations. He served as an Associate Editor for the IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2002–2003) and as a Guest Editor for the Journal of VLSI Signal Processing (Kluwer, 2004). Currently, He is a Senior Member of IEEE and a Chair of the IEEE CAS Society of the Seoul Chapter.     

Mobile Phone Antenna Performance and Power Absorption in Terms of Handset Size and Distance from User’s Head

In this work numerical simulation and measurements of three-dimensional radiation patterns of a mobile handset model in the presence of a human head phantom were performed at 1800 MHz. Based on theoretical and experimental results, the influence of the human head on the radiation efficiency of the handset has been investigated as a function of the handset size and the distance between the head and the handset during its operation. Furthermore, the relative amount of the electromagnetic power absorbed in the head has been obtained. It was found that significant reduction of the absorbed power (about 50%) with proportional increment of the handset radiation efficiency could be achieved by moving the phone for 1 cm only away from the head. Agreement between theoretical and experimental results was found to be very good.Theodore Zervos was born in Athens, Greece, on October 5, 1978. He received the diploma in Electrical & Computer Engineering from the University of Patras, Patras, Greece, in 2001. He is currently a Postgraduate Student at the Laboratory of Electromagnetics, Department of Electrical & Computer Engineering, University of Patras. He is also a doctoral scholar at the Mobile Communications Laboratory of the Institute of Informatics and Telecommunications of NCSR Demokritos, Athens. His research interests include electromagnetic modelling, EM radiation measurements and interaction between the human body and mobile handsets antenna. Dipl. T. Zervos is a Member of the Technical Chamber of Greece. In June 2002, his thesis received the 2nd Award of Excellence in Telecommunications from Ericsson.Antonis Alexandridis (1962) is senior researcher in the Institute of informatics and Telecommunications (IIT) of Greek National Research Centre (NCSR) Demokritos. He received the diploma in Electrical Engineering from Technical University ofPatras, Greece (1985), and the Ph.D. degree from the same University (1992). From 1993 he is working in the Mobile Communications Lab of NCSR. Since 1999 he is responsible for the operation of the RF Anechoic Chamber of the IIT. His current interests include mobile communications, propagation models, spread spectrum systems and CDMA techniques, EMC measurements, human exposure to EM fields, interaction between human body and mobile terminals antennas and smart antennas.Vladimir V. Petrovic was born in 1965 in Belgrade, Serbia. He received the B.Sc., M.Sc., and D.Sc., degrees from the University of Belgrade, Serbia and Montenegro in 1989, 1993, and 1996, respectively. He joined the Faculty of Electrical Engineering, University of Belgrade in 1990, where at present he is an Assistant Professor in Electromagnetics and Fundamentals of Electrical Engineering. He is a co-author of a chapter in a monograph, a software package AWAS 2.0 (Artech House – Boston, London, 2002) and several journal and conference articles. His research interests are in numerical electromagnetics, especially in radiation and propagation problems in layered media.Kostas Dangakis was born in Kavala, Greece, in 1950. He received his Diploma in Electrical Engineering from NTUA (Athens, 1973) and his Ph.D. on Digital Modulation/Data Transmission from Techn. Univ. of Patras, Dept. of Electrical Engineering (1984). Since 1977, he has worked at the Inst. of Inform. & Telecom. (IIT) of NCSR Demokritos, in projects related to voice/data/video signal encryption, synchronisation techniques in TDM systems, digital modulation techniques/data transmission, Spread Spectrum/CDMA techniques, mobile communications, conformance testing (DECT, ERMES), radio propagation, channel characterization and antennas. He is research director at IIT and has been project leader of several R & D projects.Branko M. Kolundzija Antonije R. Djordjevic was born in Belgrade, Yugoslavia, on April 28, 1952. He received the B.Sc., M.Sc., and D.Sc. degrees from the Faculty of Electrical Engineering, University of Belgrade, in 1975, 1977, and 1979, respectively. In 1975, he joined the School of Electrical Engineering, University of Belgrade, as a Teaching Assistant. He was promoted to an Assistant Professor, Associate Professor, and Professor, in 1982, 1988, and 1992, respectively. In 1983, he was a Visiting Associate Professor at Rochester Institute of Technology, Rochester, NY. Since 1992, he has also been an Adjunct Scholar with Syracuse University, Syracuse, NY. In 1997, he was elected a Corresponding Member of the Serbian Academy of Sciences and Arts. His main area of interest is numerical electromagnetics, in particular applied to fast digital signal interconnects, wire and surface antennas, microwave passive circuits, and electromagnetic-compatibility problems.C. Soras received both his diploma and Ph.D. in electrical engineering from the University of Patras, Patras, Greece, in 1981 and 1989 respectively. He was a Lecturer in the Laboratory of Electromagnetics of the Electrical and Computer Engineering department of the University of Patras in Greece from 1991 to 2001, where currently serves as an Assistant Professor. He is teaching the basic electromagnetic courses and at the senior undergraduate / graduate level computational electromagnetics. His current research interests focus on computational electromagnetics, multiple element antennas for diversity and MIMO terminal devices and indoor radio wave propagation. Prof. Soras is a member of IEEE, Applied Computational Electromagnetics Society and the Technical Chamber of Greece.     

A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes

A new parameterized-core-based design methodology targeted for programmable decoders for low-density parity-check (LDPC) codes is proposed. The methodology solves the two major drawbacks of excessive memory overhead and complex on-chip interconnect typical of existing decoder implementations which limit the scalability, degrade the error-correction capability, and restrict the domain of application of LDPC codes. Diverse memory and interconnect optimizations are performed at the code-design, decoding algorithm, decoder architecture, and physical layout levels, with the following features: (1) Architecture-aware (AA)-LDPC code design with embedded structural features that significantly reduce interconnect complexity, (2) faster and memory-efficient turbo-decoding algorithm for LDPC codes, (3) programmable architecture having distributed memory, parallel message processing units, and dynamic/scalable transport networks for routing messages, and (4) a parameterized macro-cell layout library implementing the main components of the architecture with scaling parameters that enable low-level transistor sizing and power-rail scaling for power-delay-area optimization. A 14.3 mm² programmable decoder core for a rate-1/2, length 2048 AA-LDPC code generated using the proposed methodology is presented, which delivers a throughput of 6.4 Gbps at 125 MHz and consumes 787 mW of power.Mohammad M. Mansour received his B.E. degree with distinction in 1996 and his M.S. degree in 1998 all in Computer and Communications Engineering from the American University of Beirut (AUB). In August 2002, he received his M.S. degree in Mathematics from the University of Illinois at Urbana-Champaign (UIUC). Mohammad received his Ph.D. in Electrical Engineering in May 2003 from UIUC. He is currently an Assistant Professor of Electrical Engineering with the ECE department at AUB. From 1998 to 2003, he was a research assistant at the Coordinated Science Laboratory (CSL) at UIUC. In 1997 he was a research assistant at the ECE department at AUB, and in 1996 he was a teaching assistant at the same department. From 1992–1996 he was on the Deans honor list at AUB. He received the Harriri Foundation award twice in 1996 and 1998, the Charli S. Korban award twice in 1996 and 1998, the Makhzoumi Foundation Award in 1998, and the PHI Kappa PHI Honor Society awards in 2000 and 2001. During the summer of 2000, he worked at National Semiconductor Corp., San Francisco, CA, with the wireless research group. His research interests are VLSI architectures and integrated circuit (IC) design for communications and coding theory applications, digital signal processing systems and general purpose computing systems.Naresh R. Shanbhag received the B.Tech from the Indian Institute of Technology, New Delhi, India, in 1988, M.S. from Wright State University and Ph.D. degree from the University of Minnesota, in 1993, all in Electrical Engineering. From July 1993 to August 1995, he worked at AT&T Bell Laboratories at Murray Hill in the Wide-Area Networks Group, where he was responsible of development of VLSI algorithms, architectures and implementation for high-speed data communications applications. In particular, he was the lead chip architect for AT&Ts 51.84 Mb/s transceiver chips over twisted-pair wiring for Asynchronous Transfer Mode (ATM)-LAN and broadband access. Since August 1995, he is with the Department of Electrical and Computer Engineering, and the Coordinated Science Laboratory where he is presently an Associate Professor and Director of the Illinois Center for Integrated Microsystems. At University of Illinois, he founded the VLSI Information Processing Systems (ViPS) Group, whose charter is to explore issues related to low-power, high-performance, and reliable integrated circuit implementations of broadband communications and digital signal processing systems. He has published numerous journal articles/book chapters/conference publications in this area and holds three US patents. He is also a co-author of the research monograph Pipelined Adaptive Digital Filters (Norwell, MA: Kluwer, 1994). Dr. Shanbhag received the 2001 IEEE Transactions Best Paper Award, 1999 Xerox Faculty Research Award, 1999 IEEE Leon K. Kirchmayer Best Paper Award, the 1997 Distinguished Lecturer of IEEE Circuit and Systems Society (97–99), the National Science Foundation CAREER Award in 1996, and the 1994 Darlington Best Paper Award from the IEEE Circuits and Systems society. From 1997–99 and 2000–2002, he served as an Associate Editor for IEEE Transaction on Circuits and Systems: Part II and an Associate Editor for the IEEE Transactions on VLSI, respectively. He was the technical program chair for the 2002 IEEE Workshop on Signal Processing Systems (SiPS02).     

A Broadband Double-Conversion RF Tuner

A prototype design of upconverter and downconverter units for a double-conversion cable-modem RF tuner are presented. The upconverter upconverts a channel from 47–862 MHz input band to around 1575 MHz intermediate frequency. The image-reject downconverter shifts the channel to 36.125 MHz (EU) or to 43.75 MHz (US). The upconverter includes a variable-gain low-noise amplifier, a double-balanced mixer, a three-stage VCO bank for LO generation and a divide-by-two circuit for driving an external PLL. The downconverter includes a LNA, image-reject mixers in Hartley configuration, a 3-stage polyphase filter, an IF-amplifier and a SAW driver. For the second LO generation the circuit includes a 6-GHz on-chip VCO, a divide-by-four circuit for quadrature LO and a divide-by-16 for feeding an external PLL. Signal reversal switching in the LO buffer can be used for the selection of LSB/USB injection. All building blocks are presented in this paper and experimental results are given from the upconverter, downconverter, and RF tuner demonstrator including SAW filters with center frequencies at 1575 and 44 MHz. The circuits are fabricated in a 0.9- m SiGe bipolar process.Kari Stadius received the M.Sc. degree in electrical engineering in 1994 and the Licentiate of Technology degree in 1997, both from Helsinki University of Technology, where he is currently working as a research scientist. His research interests include the design and analysis of RF transceiver blocks with special emphasis on RF oscillators and modelling of passive components.Arto Malinen was born in Savonlinna, Finland, in 1978. He received the M.Sc. degree in electrical engineering from the Helsinki University of Technology (HUT), Finland, in 2003, where he is currently working towards the Ph.D. degree. He is a research engineer with the Electronic Circuit Design Laboratory, HUT. His main research interests are in RF IC design, including low-noise amplifiers and mixers.Petri S. Järviö was born in Kitee on December 10, 1975. He received the M.Sc (EE) degree in 2001 from the Helsinki University of Technology. From 1999 to 2001 he worked as a research assistant at the Electronic Circuit Design Laboratory in Helsinki University of Technology. Nowadays he works at Finnish Defence Forces Technical Research Centre, Electronics and Information Technology Division where his research area is Radio frequency sensors.Kari A.I. Halonen was born in Helsinki, Finland, in 1958. He received the M.Sc. degree in electrical engineering from Helsinki University of Technology, Finland, in 1982, and the Ph.D. degree in electrical engineering from the Katholieke Universiteit Leuven, in Heverlee, Belgium, in 1987. From 1982 to 1984 he was employed as assistant at Helsinki University of Technology and as research assistant at the Technical Research Centre of Finland. From 1984 to 1987 he was research assistant at the E.S.A.T. Laboratory of the Katholieke Universiteit Leuven, enjoying also a temporary grant of the Academy of Finland. Since 1988 he has been with the Electronic Circuit Design Laboratory, Helsinki University of Technology, as senior assistant (1988–1990), and the director of the Integrated Circuit Design Unit of the Microelectronics Centre (1990–1993). He was on leave of absence the academic year 1992/93, acting as R{&}D manager in Fincitec Inc., Finland. From 1993 to 1996 he has been an associate professor, and since 1997 a full professor at the Faculty of the Electrical Engineering and Telecommunications, Helsinki University of Technology. He specializes in CMOS and BiCMOS analog integrated circuits, particularly for telecommunication applications. He is author or co-author of a hundred international and national conference and journal publications on analog integrated circuits.     

An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems

The implementation of the memory for storing image and transform coefficients in 2-D DWT processing systems using the more cost-effective external memory module such as DDR DRAM is shown to suffer from effective memory bandwidth which is significantly lower than the memory system peak bandwidth if the conventional direct logical-to-physical memory address mapping is adopted. The low effective memory bandwidth is caused by the high level of memory overhead cycle occurrence which is in turn is closely related to the logical memory access patterns of 2-D DWT processes. The problem becomes even more severe for the 2-D DWT processing of video. An analysis on the logical memory access patterns of multi-level 2-D DWT is carried out and an enhanced logical-to-physical memory mapping scheme which minimizes the occurrence of memory overhead cycles is proposed. The proposed scheme is simulated and its performance in terms of effective memory access bandwidth is evaluated and compared with the conventional direct mapping scheme.

An On-Chip Spectrum Analyzer for Analog Built-In Testing

This paper presents an analog built-in testing (BIT) architecture and its implementation. It enables the frequency response and harmonic distortion characterizations of an integrated device-under-test (DUT) through a digital off-chip interface. External analog instrumentation is avoided, reducing test time and cost. The proposed on-chip testing scheme uses a digital frequency synthesizer and a simple signal generator synchronized with a switched capacitor bandpass filter. A general methodology for the use of this structure in the functional verification of a DUT is also provided. The circuit-level design and experimental results of an integrated prototype in standard CMOS 0.5 m technology are presented to demonstrate the feasibility of the proposed BIT technique.Marcia G. Mendez-Rivera was born in Irapuato, Mexico in 1972. She received the Communications and Electronics Engineering Degree from the Universidad de Guanajuato, Guanajuato, Mexico. in 1996, the M.Sc. degree from the Instituto Nacional de Astrofisica, Optica y Electronica (INAOE), Puebla, Mexico in 1998 and the M.Sc. from Texas A&M University, College Station in 2002. Her research interest is in the design and fabrication of analog and mixed-signal circuits.Alberto Valdes-Garcia born in 1978, grew up in San Mateo Atenco, Mexico. He received the B.S. in Electronic Systems Engineering degree from the Monterrey Institute of Technology (ITESM), Campus Toluca, Mexico in 1999 (with honors as the best score from all majors). Since the fall of 2000 he has been working towards the Ph.D. degree at Analog and Mixed-Signal Center (AMSC), Texas A&M University. During the spring and summer of 2000 he was a Design Engineer with Motorola Broadband Communications Sector. In the summer of 2002 he was with the Read Channel Design Group at Agere Systems where he investigated wide tuning range GHz LC VCOs for mass storage applications. During the summer of 2004 he was with the Mixed-Signal Communications IC Design Group at the IBM T. J. Watson Research Center, where worked on design and analysis of SiGe power amplifiers for millimeter wave radios. Since the fall of 2001 he has been a Semiconductor Research Corporation (SRC) research assistant at the AMSC working on the development of analog built-in testing techniques. Since the fall of 2000, Alberto has been the recipient of a scholarship from the Mexican National Council for Science and Technology (CONACYT). He represented Mexico in the 1994 Odyssey of the Mind World Creativity Contest and in the 1997 International Exposition for Young Scientists. His present research interests include built-in testing implementations for analog and RF circuits, system level design for wireless receivers and RF circuit design for UltraWideBand (UWB) communications.Jose Silva-Martinez was born in Tecamachalco, Puebla, México. He received the B.S. degree in electronics from the Universidad Autónoma de Puebla, México, in 1979, the M.Sc. degree from the Instituto Nacional de Astrofísica Optica y Electrónica (INAOE), Puebla, México, in 1981, and the Ph.D. degree from the Katholieke Univesiteit Leuven, Leuven Belgium in 1992. From 1981 to 1983, he was with the Electrical Engineering Department, INAOE, where he was involved with switched-capacitor circuit design. In 1983, he joined the Department of Electrical Engineering, Universidad Autonoma de Puebla, where he remained until 1993; He was a co-founder of the graduate program on Opto-Electronics in 1992. From 1985 to 1986, he was a Visiting Scholar in the Electrical Engineering Department, Texas A&M University. In 1993, he re-joined the Electronics Department, INAOE, and from May 1995 to December 1998, was the Head of the Electronics Department; He was a co-founder of the Ph.D. program on Electronics in 1993. He is currently with the Department of Electrical Engineering (Analog and Mixed Signal Center) Texas A&M University, at College Station, where He holds the position of Associate Professor. His current field of research is in the design and fabrication of integrated circuits for communication and biomedical application. Dr. Silva-Martinez has served as IEEE CASS Vice President Region-9 (1997–1998), and as Associate Editor for IEEE Transactions on Circuits and Systems part-II from 1997–1998 and May 2002–December 2003. Since January 2004 is serving as Associate Editor of IEEE TCAS Part-I. He was the main organizer of the 1998 and 1999 International IEEE-CAS Tour in region 9, and Chairman of the International Workshop on Mixed-Mode IC Design and Applications (1997–1999). He is the inaugural holder of the TI Professorship-I in Analog Engineering, Texas A&M University. He was a co-recipient of the 1990 European Solid-State Circuits Conference Best Paper Award.Edgar Sánchez-Sinencio was born in Mexico City, Mexico. He received the degree in communications and electronic engineering (Professional degree) from the National Polytechnic Institute of Mexico, Mexico City, the M.S.E.E. degree from Stanford University, CA, and the Ph.D. degree from the University of Illinois at Urbana-Champaign, in 1966, 1970, and 1973, respectively. In 1974 he held an industrial Post-Doctoral position with the Central Research Laboratories, Nippon Electric Company, Ltd., Kawasaki, Japan. From 1976 to 1983 he was the Head of the Department of Electronics at the Instituto Nacional de Astrofísica, Optica y Electrónica (INAOE), Puebla, Mexico. He was a Visiting Professor in the Department of Electrical Engineering at Texas A&M University, College Station, during the academic years of 1979–1980 and 1983-1984. He is currently the TI J Kilby Chair Professor and Director of the Analog and Mixed-Signal Center at Texas A&M University. He was the General Chairman of the 1983 26th Midwest Symposium on Circuits and Systems. He was an Associate Editor for IEEE Trans. on Circuits and Systems, (1985–1987), and an Associate Editor for the IEEE Trans. on Neural Networks. He is the former Editor-in-Chief of the Transactions on Circuits and Systems II. He is co-author of the book Switched Capacitor Circuits (Van Nostrand-Reinhold 1984), and co-editor of the book Low Voltage/Low-Power Integrated Circuits and Systems (IEEE Press 1999). In November 1995 he was awarded an Honoris Causa Doctorate by the National Institute for Astrophysics, Optics and Electronics, Mexico. The first honorary degree awarded for Microelectronic Circuit Design contributions. He is co-recipient of the 1995 Guillemin-Cauer for his work on Cellular Networks. He is a former IEEE CAS Vice President-Publications. He was also the co-recipient of the 1997 Darlington Award for his work on high-frequency filters He received the Circuits and Systems Society Golden Jubilee Medal in 1999. He was the IEEE Circuits and Systems Society, Representative to the Solid-State Circuits Society (2000–2002). He is presently a member of the IEEE Solid-State Circuits Fellow Award Committee. His present interests are in the area of RF-Communication circuits and analog and mixed-mode circuit design. He is an IEEE Fellow Member since 1992.     

Configurable Data Memory for Multimedia Processing

In modern multimedia applications, memory bottleneck can be alleviated with special stride data accesses. Data elements in stride access can be retrieved in parallel with parallel memories, in which the idea is to increase memory bandwidth with several memory modules working in parallel and feed the processor with only necessary data. Arbitrary stride access capability with interleaved memories is described in previous research where the skewing scheme is changed at run time according to the currently used stride. This paper presents the improved schemes which are adapted to parallel memories. The proposed novel parallel memory implementation allows conflict free accesses with all the constant strides which has not been possible in prior application specific parallel memories. Moreover, the possible access locations are unrestricted and the accessed data element count equals to the number of memory modules. Timing and area estimates are given for Altera Stratix FPGA and 0.18 micrometer CMOS process with memory module count from 2 to 32. The FPGA results show 129 MHz clock frequency for a system with 16 memory modules when read and write latencies are 3 and 2 clock cycles, respectively. The complexity of the proposed system is shown to be a trade-off between application specific and highly configurable parallel memory system.     

Differentially-Tuned VCO with Reduced Tuning Sensitivity and Flicker Noise Up-Conversion

Differential tuning in oscillators allows cancellation of common-mode bias noise and lower tuning sensitivity with respect to the most conventional single-ended tuning. However, the direct application of differential tuning increases the capacitor non-linearity and the flicker-induced phase noise. This paper analyzes quantitatively this phenomenon and proposes a novel configuration, which includes all the benefits of differential tuning with no penalty on phase noise. This circuit is fabricated in a 0.35-m CMOS technology together with a single-end-tuned oscillator and both cover the 2.0–2.4 GHz frequency range. The measured 1/f³ phase noise at 10 kHz offset is –71 dBc/Hz, which outperforms the companion single-end tuning oscillator by 10 dB.A.L. Lacaita is also with IFN-CNR Sezione Milano.Salvatore Levantino was born in 1973. He received the degree of Ingegnere in 1998 and the Ph.D. degree in electrical engineering in 2001 from the Politecnico di Milano, Italy. During his PhD program, he studied noise generation mechanisms in integrated oscillators and novel topologies for agile frequency synthesis. He also spent one year at Agere Systems (formerly Bell Laboratories), Murray Hill, NJ, working as consultant on IF-sampling receiver architectures. Since 2002, he is a post-doctoral researcher at the Politecnico di Milano. His research interests are mainly focused on fully integrated transceivers for wireless applications.Andrea Bonfanti was born in Besana B.za (Milan), Italy, in 1972. He received the Laurea Degree and the Ph.D. in electronics engineering from the Politecnico di Milano, Italy, in 1999 and in 2002, respectively. Since 2003, he is a post-doctoral researcher at the Politecnico di Milano. His activity is focused on the design of frequency synthesizers for wireless applications in CMOS. His research interests also include analog-to-digital converters.Luca Romanó was born in Milan, Italy, in 1976. He received the Laurea Degree in electronics engineering from the Politecnico di Milano, Milan, Italy, in 2001. He is currently working toward the Ph.D. degree in electronics and communications at the Politecnico di Milano. His research activity is oriented towards the development of frequency synthesizers for wireless broadband communications.Carlo Samori was born in 1966, in Perugia, Italy. He received the Laurea Degree in electronics engineering in 1992, and the Ph.D. in electronics and communications at the Politecnico di Milano, Italy, in 1995. In 2002, he was appointed Associate Professor of Electronics at the Politecnico di Milano. He worked on solid-state photo-detector and the associated front-end electronics. His current research interests include design and analysis of integrated circuits for communications in bipolar and CMOS technologies, noise analysis in oscillators, frequency synthesizer architectures. Since 1997, he is a Consultant of the Wireless Communication Circuit Research Department of Agere Systems, Murray Hill.Andrea L. Lacaita was born in 1962. He received the Laurea degree in nuclear engineering from the Politecnico di Milano, Italy, in 1985. In 1989–90, he was Visiting Scientist at the AT&T Bell Laboratories, Murray Hill, NJ, working on photo-refractive effects in superlattices for optical switching. In 1992, he became Associate Professor of Electronics at the Politecnico of Milano and since then, he has been teaching courses on electronics, electron devices, optoelectronics and solid-state physics. In 1999, he has been Academic Visitor at IBM T.J. Watson Research Center, Yorktown Heights, NY, where he contributed to the development of optical systems for IC testing. In 2000, he was appointed Full Professor of Electronics at the Politecnico di Milano and Head of the Microelectronics Lab. As researcher, he contributed to analog IC design with studies of phase noise in integrated LC-tuned oscillators and with the development of novel architectures of frequency synthesizers in RF front-ends. He has contributed to advances in microelectronics and optoelectronics, with particular emphasis on physics of single photon avalanche detectors, characterization and modeling of semiconductor devices. Within the field of ULSI microelectronics, he has studied carrier transport and quantum effect in scaled MOS transistors, technology and reliability of non-volatile memories. He is co-author of about 150 papers published in journals or presented in international conferences. He is also author of two books in Electronics.Prof. Lacaita received in 1993 the Award of the Italian Association of Electrical and Electronic Engineers (AEI) for his research on hot carrier effects. In 1998–2000, he served as Coordinator of the Committee on micro-and nano-electron devices of the Italian National Group of Electronics Engineers. Since 2000, he has been consultant for the European Commission in the evaluation on review of research projects in micro- and nano-electronics. Since 2001, he has been serving in the program committee of the IEEE International Electron Device Meeting (IEDM) and he is now European Chair.     

A Generalized Analytical Framework for SMPT in a Multicode CDMA Wireless System

Simultaneous MAC Packet Transmission (SMPT) has recently been proposed for stabilizing the throughput over wireless links, which is one of the key challenges in providing high-quality wireless multimedia services. SMPT stabilizes the wireless link by transmitting multiple packets on multiple CDMA channels in parallel in response to packet drops due to wireless link errors. These parallel packet transmissions stabilize the link layer throughput, but they also increase the interference level in a given cell of a cellular network or cluster of an ad-hoc network, which in turn reduces the number of traffic flows that can be simultaneously supported in a cell/cluster. We have recently developed an analytical framework for the class of SMPT mechanisms for a simple Bernoulli packet generation process, which does not reflect the oftentimes bursty packet generation processes encountered in real networks. In this paper we develop a generalized analytical framework for SMPT, which accommodates bursty packet traffic (and also non-bursty Bernoulli traffic). This framework expresses the system dynamics in transition probabilities for a Markov chain and calculates the effects of the interference through an iterative approach. The numerical results from our analytical framework and verifying simulations indicate that SMPT provides a significant reduction in packet loss and buffer occupancies (and delay), especially for persistent traffic bursts, in exchange for a reduced number of supported flows. Our analytical framework quantifies these system trade-offs with good accuracy and can thus be employed for resource management.Manjunath Krishnam received the B.E. degree in Electronics and Communications from R.V. College of Engineering, Bangalore University, Bangalore, India, in 1996, the M.S. degree and Ph.D. degree in Electrical Engineering from Arizona State University, Tempe, AZ, in 1999 and 2004 respectively. His research interests are in the areas of network performance analysis, network and traffic modeling, and resource management in wireless networks. Mr. Krishnam is a member of IEEE.Martin Reisslein is an Assistant Professor in the Department of Electrical Engineering at Arizona State University, Tempe. He is affiliated with ASUs Wireless Integrated Nano Technologyy (WINTech) center. He received the Dipl.-Ing. (FH) degree from the Fachhochschule Dieburg, Germany, in 1994, and the M.S.E. degree from the University of Pennsylvania, Philadelphia, in 1996. Both in electrical engineering. He received his Ph.D. in systems engineering from the University of Pennsylvania in 1998. During the academic year 1994–1995 he visited the University of Pennsylvania as a Fulbright scholar. From July 1998 through October 2000 he was a scientist with the German National Research Center for Information Technology (GMD FOKUS), Berlin. While in Berlin he was teaching courses on performance evaluation and computer networking at the Technical University Berlin. He is editor–in–chief of the IEEE Communications Surveys and Tutorials and has served on the Technical Program Committees of IEEE Infocom, IEEE Globecom, and the IEEE International Symposium on Computer and Communications. He has organized sessions at the IEEE Computer Communications Workshop (CCW). He maintains an extensive library of video traces for network performance evaluation, including frame size traces of MPEG–4 and H.263 encoded video, at He is co–recipient of the Best Paper Award of the SPIE Photonics East 2000—Terabit Optical Networking conference. His research interests are in the areas of Internet Quality of Service, video traffic characterization, wireless networking, and optical networking.     

A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System

The Data-Intensive Architecture (DIVA) system employs Processing-In-Memory (PIM) chips as smart-memory coprocessors. This architecture exploits inherent memory bandwidth both on chip and across the system to target several classes of bandwidth-limited applications, including multimedia applications and pointer-based and sparse-matrix computations. The DIVA project has built a prototype development system using PIM chips in place of standard DRAMs to demonstrate these concepts. We have recently ported several demonstration kernels to this platform and have exhibited a speedup of 35X on a matrix transpose operation.This paper focuses on the 32-bit scalar and 256-bit WideWord integer processing components of the first DIVA prototype PIM chip, which was fabricated in TSMC 0.18 m technology. In conjunction with other publications, this paper demonstrates that impressive gains can be achieved with very little smart logic added to memory devices. A second PIM prototype that includes WideWord floating-point capability is scheduled to tape out in August 2003.Jeffrey Draper is a Research Assistant Professor in the Department of Electrical Engineering at the University of Southern California. He holds this appointment in conjunction with a Project Leader position at the Information Sciences Institute of the University of Southern California. Dr. Drapers research group has participated in many DARPA-sponsored large-scale VLSI development efforts. He is a member of the IEEE Computer Society and has conducted research in the areas of processing-in-memory architectures, thermal management, VLSI, interconnection networks, and modeling/performance evaluation. Dr. Draper received a BSEE from Texas A&M University and an MS and PhD from the University of Texas at Austin.J. Tim Barrett is a Senior Electrical Engineer at the Information Sciences Institute of the University of Southern California. Mr. Barrett has managed, designed and implemented the hardware, low-level software and integration of many computer systems. Applications of these systems include scalable supercomputers at USC Information Sciences Institute, the long distance telephone switch at AT&T Bell Labs, building energy management at Barber-Colman Company, and laser entertainment performance instruments at Aura Technologies and Laser Images Inc. He is a member of IEEE Solid State Circuits Society and received his MSCS from the University of Illinois Chicago and BSEE from the University of Iowa.Jeff Sondeen is a Research Associate at the Information Sciences Institute of the University of Southern California, where he supports and maintains CAD technology files, libraries, and tools for implementing VLSI designs. Previously he has worked at Silicon Compilers and Hewlett-Packard in CAD tool and test chip development. He received an MSEE from the University of Michigan.Sumit Mediratta is currently pursuing a PhD in Electrical Engineering at the University of Southern California. He received a Bachelor of Engineering degree in Electronics and Telecommunication from the Shri Govind Ram Sekseria Institute of Technology and Science, India. His research interests include interconnection networks, VLSI, processing-in-memory architectures, high-speed data communication and synchronization techniques and network interfaces for high-performance architectures.Chang Woo Kang received a BS in electrical engineering from Chung-ang University, Seoul, South Korea, in 1997 and an MS in electrical engineering from the University of Southern California, Los Angeles, in 1999. He is currently pursuing a PhD in electrical engineering at the University of Southern California. His research includes VLSI system design and algorithms for low-power logic synthesis and physical design.Ihn Kim is a PhD student in the Department of Electrical Engineering at the University of Southern California. He is also a Staff Engineer at QLogic. His research interests include user-level network interface, network processor architectures, and modeling/performance evaluation of system area networks. He is a member of the IEEE Computer Society. He received an MS at KAIST (Korea Advanced Institute of Science and Technology).Gokhan Daglikoca is an Application Engineer at Cadence Design Systems, Inc, where he specializes in High-Performance ASIC and Microprocessor Design Methodologies. He is a member of IEEE. Gokhan Daglikoca received a BS from Istanbul Technical University and an MS from the University of Southern California.