Threshold shift of p-channel transistors by boron implantation and the C-V characteristics of the corresponding mos structures

Short p-channel transistors for scaled CMOS circuits are fabricated using double implantations with phosphorus and boron ions. Deep phosphorus channel implantation is required for increasing the channel punch-through voltage, while shallow boron implantation is used to adjust the device threshold voltage for p-channel transistors with n + poly as the gate electrode. The effect of the boron dose and the sub-surface junction depth on the device characteristics, especiallly the C?V characteristics, is investigated.The capacitance dispersion with respect to frequency, which is observed for MOS diodes with large boron dose or deep boron depth, will be discussed in detail. This phenomenon is explained by the majority carrier modulation at the sub-surface junction associated with the boron implanted channel. The effect of the non-uniform phosphorus channel doping on the measured C?V characteristics will also be examined. The technique of the one-dimensional calculation of the channel potential distribution is presented to show the correlation of the implanted boron dose and the observed abnormal C?V characteristics.     

Design and analysis of noise margin,write ability and read stability of organic and hybrid 6-T SRAM cell

This paper analyzes SRAM cell designs based on organic and inorganic thin film transistors (TFTs). The performance in terms of static noise margin (SNM), read stability and write ability for all-p organic (Pentacene–Pentacene), organic complementary (Pentacene–C₆₀) and hybrid complementary (Pentacene–ZnO) configurations of SRAM cell is evaluated using benchmarked industry standard Atlas 2-D numerical device simulator. Moreover, the cell behaviour is analyzed at different cell and pull-up ratios. The electrical characteristics and performance parameters of individual TFT used in SRAM cell is verified with reported experimental results. Furthermore, the analytical result for SNM of all-p organic SRAM cell is validated with respect to the simulated result. Besides this, the cell and pull-up ratios of the hybrid and organic SRAM cells are optimized for achieving best performance of read and write operations and thereafter, the results are verified analytically also. The SNM of hybrid cell is almost two times higher than the all-p SRAM, whereas this improvement is just 18% in comparison to the organic memory cell. On the other hand, the organic complementary SRAM cell shows an improvement of 26% and 22% for the read stability in comparison to the all-p organic and hybrid SRAM cells, respectively. Contrastingly, this organic cell demonstrates a reduction of 16% in the SNM and an increment of 76% in write access time in comparison to the hybrid cell. To achieve an overall improved performance, the organic complementary SRAM cell is designed such that the access transistors are pentacene based p-type instead of often used n-type transistor. Favorably, this organic SRAM design shows reasonably lower write access time in comparison to the cell with n-type access OTFTs. Moreover, this cell shows adequate SNM and read stability that too at substantially lower width of p-type access OTFTs.     

Study of RF transistor with submicron T-shaped gate fabricated by nanoimprint lithography

The results devoted to the development of a method for creating an RF transistor, in which a T-shaped gate is formed by nanoimprint lithography, are presented. The characteristics of GaAs p-HEMT transistors have been studied. The developed transistor has a gate “foot” length of the order of 250 nm and a maximum transconductance of more than 350 mS/mm. The maximum frequency of current amplification f _t is 40 GHz at the drain-source voltage V _DS = 1.4 V and the maximum frequency of the power gain f _max is 50 GHz at V _DS = 3 V.     

Simulation of electrical characteristics of InP double-heterojunction bipolar transistors with InGaAsSb base

We study the effect of antimony (Sb) content in the InGaAsSb base layer of InP double-heterojunction bipolar transistors (DHBTs), under the condition of lattice match, by using a two-dimensional device simulator Medici. Careful calibration of physical parameters is first done to ensure that the simulation result matches data measured from a reference device. When the composition of Sb in the InGaAsSb base region is varied, the conduction band offset (ΔE_C), effective density of states in conduction band and valence band (N_C, N_V), bandgap energy (E_G), and intrinsic carrier concentration (n_i) are changed accordingly. These semiconductor material parameters are considered in the simulation to compare the electrical characteristics of the DHBT. In addition to the Sb composition, different materials of In_0.52Al_0.48As or InP in the emitter are simulated. The study on Sb content in the base and the heterostructure of E-B junction helps the development and optimization of InGaAsSb DHBTs.     

A new integrated voltage-controlled negative resistance device-Lambda MOSFET

A new Λ-type voltage-controlled negative resistance device called the “Lambda MOSFET” is presented, which consists of three integrated n(p)-channel enhancement mode metal-oxide-silicon field effect transistors. The main integrated circuit construction of the Lambda MOSFET is to connect an inverter of the n(p)-channel enhancement mode MOSFET with load operated at the saturation region (NELS) and a n(p)-MOS driver, which can be easily fabricated by existing planar MOSFET technologies. The operational principles and the characteristics of the proposed new device are discussed.     

Modeling silicon emitters for VLSI transistors

The accuracy and reliability of predictions from numerical simulations of advanced bipolar transistors for VLSI applications depend on model input parameters. These parameters include the variations with doping and carrier concentrations in both n-type and p-type silicon of (1) the valance and conduction band edges, (2) the effective intrinsic carrier concentrations, (3) the minority carrier mobilities, and (4) the minority carrier lifetimes. This paper reviews recent advances in device physics for modeling the emitters of bipolar transistors with submicrometer dimensions and high concentrations of dopant ions and carriers.     

Effects of varying the processing parameters on the interface-state density and retention characteristics of an MNOS capacitor

The p⁺-gridded MNOS capacitor was fabricated to facilitate the study of the effects of Write/Erase cycling and of varying the processing parameters on the interface-state density in an MNOS nonvolatile memory device. A model is derived for this device, which enables the extraction of the device parameters using the quasi-static C−V (QSCV) technique. The distribution of the interface-state density across the forbidden energy gap of silicon was deduced from QSCV measurements. Interface-state density minima between 1.8 × 10¹¹ and 9.1 × 10¹¹eV⁻¹cm⁻² near the silicon midgap were obtained. The effects of processing variations on the Si/SiO₂ interface-state density distribution and the retention characteristics of the MNOS were studied.     

Planar,ion-implanted bipolar devices in GaAs

Selected-area ion implantation using heavy metal masks to define the device geometry has been used to fabricate doubly implanted npn bipolar transistors and planar, isolated pn junction devices in GaAs. The bipolar transistors exhibited common-emitter current gains as high as 25. Collector-base breakdown voltages of 45 V were observed. The junction diodes (～200 um dia.) exhibited sub-nanoampere leakage currents at 15 V of reverse bias. Surface leakage appears to be the dominant mechanism responsible for the observed leakage currents. The diode forward current is limited by recomination in the space charge region.     

Effect of the initial stage of film growth on device performance of organic transistors based on dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT)

The initial stage of organic film growth is considered to be vital for the carrier transport in organic thin-film transistors with bottom gate configuration. The same topographies of 40 nm dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) films on para-sexiphenyl (p-6P) monolayer and bare SiO₂ exhibited quite different field-effect mobilities, 1.9 and 0.1 cm²/V s, respectively. The further investigation indicated there were different growth behaviors at their initial stages of film growth. Column islands with high density were observed on SiO₂, while lamina islands on p-6P monolayer due to the good diffusion ability and their good epitaxial relationship. The latter is beneficial to obtain high quality film with less boundaries and defects. The work demonstrated that the initial stage of film growth is an important factor to determine the device performance of organic transistors, which is significant to improve the device fabrication and optimize the device performance.     

Single and dual gate OTFT based robust organic digital design

This paper analyzes and compares the performance of the single gate (SG) and dual gate (DG) organic thin film transistors (OTFTs) based inverter circuits. The DG-OTFT device performs better than SG-OTFT mainly in terms of mobility, on–off current ratio and sub-threshold slope. The mobility of DG device is almost five times higher than the SG, while, an increase of 74% in on–off current ratio and a decrease of 41% in sub-threshold slope are observed. Two different configurations of inverter circuits i.e. diode-load logic (DLL) and zero-V_gs-load logic (ZVLL) are studied. The static and dynamic behaviors of the p-type DLL and ZVLL inverters using SG and DG organic transistors are observed. The DG-OTFT improves gain and noise margins for both DLL and ZVLL inverter circuits. Using DG device, propagation delay reduces by 59% for DLL and 42% for ZVLL as compared to SG OTFT based configurations. Moreover, fixed back gate bias technique further enhances the noise margin and gain by 8% and 18% for DLL and 19% and 26% for ZVLL configurations, respectively. Finally, bootstrapping technique is also applied to the dual gate inverters that further boosts the noise margin and gain for DLL and ZVLL configurations.     

Static and dynamic analysis of amorphous-silicon field-effect transistors

Analytical expressions have been developed for the analysis of static and dynamic behaviour of hydrogenated-amorphous-silicon based field-effect transistors. The current/voltage, capacitances and transcapacitances/voltage characteristics are related to the material parameters. The characteristic temperature, T_c, of the exponential band-tail states distribution is shown to influence strongly their shape and magnitude. An exact integration of the potential in the structure has allowed us to give expressions for the source and drain resistances. Finally, we present an equivalent circuit of a-Si:H TFT which can be employed in circuit simulation for the optimisation of integrated circuits.     

垂直隧穿场效应晶体管的亚阈值特性分析

Subthreshold characteristics of vertical tunneling field effect transistors(VTFETs) with an nC-pocket in the pC-source are studied by simulating the transfer characteristics with a commercial device simulator.Three types of subthreshold characteristics are demonstrated for the device with different pocket thicknesses and doping concentrations.Band diagram analysis shows that such a VTFET can be treated as a gate-controlled tunnel diode connected in series with a conventional n-channel metal-oxide-semiconductor FET.This VTFET can work either as a TFET or an n-MOSFET in the subthreshold region,depending on the turn-on sequence of these two components.To our knowledge,this is the first time such a device model has been used to explain the subthreshold characteristics of this kind of VTFET and the simulation results demonstrate that such a device model is convictive and valid.Our results indicate that the design of the nC pocket is crucial for such a VTFET in order to achieve ultra-steep turn-on characteristics.     

A computer-aided analysis of one-dimensional thermal transients in n-p-n power transistors

An algorithm is presented which permits the one-dimensional simulation of thermal transients in n-p-n transistors. Band distortion effects, temperature dependent mobilities and thermal conductivity are incorporated into the model. Accurate expressions are derived for the heat generated at any point within the semiconductor and the finite difference forms of the current continuity equations. Results showing the internal device behaviour under various bias conditions are presented.     

Theory of switching in p-n-insulator (tunnel)-metal devices: Part I: Punchthrough mode

The four-layered structure (M-I(leaky)-n-p⁺) is found to exhibit a current-controlled negative resistance region in its I-V characteristics. In this paper, a quantitative physical model of the device in the punch-through mode is presented. The negative resistance behaviour is due to a positive feedback mechanism between the tunnel MIS and the n-p⁺ junction parts of the device. The effect of the device parameters on its I-V characteristics is studied.     

SPICE modelling of hot-carrier degradation in Si1–xGex S/D and HfSiON based pMOS transistors

Hot-carrier degradation in pMOS transistors with Si_1–xGe_x implantations in the source and drain areas is analyzed (SiGe S/D). A simulation methodology is developed to translate the effects to circuit simulators. This methodology is applied to study hot-carrier degradation in CMOS inverters designed with SiGe S/D pMOS transistors. The results show that although pMOS transistors with embedded SiGe S/D have a better device performance, these devices are more sensitive to hot-carrier degradation at both the device and circuit levels.     

Scaling limits of organic digital circuits

The effect of device scaling on organic circuits’ performance was studied. Particularly, the influence of contact resistance on the static and the dynamic behavior of the circuits was investigated. For that purpose, an analytical model describing the voltage transfer characteristics (VTCs) and the propagation delay was developed. Using the model, it was shown that for OTFTs with channel lengths of less than 10 μm the contact resistance has negative influence on both, the static noise margin (SNM) and the propagation delay. Moreover, the model is in a good agreement with experimentally measured data. Scaling the lateral dimensions of the transistors down to few μm limits the circuit performance due to contact effects, and the 1–10 MHz frequency range operation required by some applications can only be achieved by reducing the specific contact resistance, ρ_c, 10–100 times. This need for ρ_c reduction highlights the importance of improving charge injection in organic transistors that can usually be achieved by contact doping like in inorganic electronics.     

Extraction of electronic parameters of Schottky diode based on an organic Orcein

An Au/Orcein/p-Si/Al device was fabricated and the current-voltage measurements of the devices showed diode characteristics. Then the current-voltage (I-V), capacitance-voltage (C-V) and capacitance-frequency (C-f) characteristics of the device were investigated at room temperature. Some junction parameters of the device such as ideality factor, barrier height, and series resistance were determined from I-V and C-V characteristics. The ideality factor of 2.48 and barrier height of 0.70 eV were calculated using I-V characteristics. It has been seen that the Orcein layer increases the effective barrier height of the structure since this layer creates the physical barrier between the Au and the p-Si. The interface state density N_ss were determined from the I-V plots. The capacitance measurements were determined as a function of voltage and frequency. It was seen that the values of capacitance have modified with bias and frequency.     

Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach

We present the monolithic integration of gate-all-around (GAA) Si-nanowire FETs into CMOS logic using top-down approach. Inverters are chosen as the test vehicles for demonstration. Empirically optimized designs show sharp ON–OFF transitions with high voltage-gains (e.g., ΔV_OUT/ΔV_IN up to ～45) and symmetric pull-up and pull-down characteristics. The matching of the drive currents of n- and p-MOSFETs is achieved using different number of nanowire channels for N- and P-MOS transistors. The inverter maintains its good transfer characteristics and noise margins for wide range of V_DD tested down to 0.2 V. The detailed experimental characterization is discussed along with the electrical characteristics of the individual transistors comprising the inverter. The performances of the inverters are discussed vis-à-vis those reported in the literature using advanced non-classical device architectures such as FinFETs. The integration potential of GAA Si-nanowire transistors to realize CMOS circuit functionality using top-down approach is thus demonstrated.     

Numerical CML switching analyses for heterojunction GaAs/(GaAl)As bipolar transistors

The switching performance of GaAs/Ga_0.7Al_0.3As n-p-n heterojunction bipolar transistors (HBTs) has been investigated for current-mode-logic circuit operation using a hybrid device model composed of numerical one-dimensional transistor and diode models interconnected through resistances corresponding to the real device structure.Switching time is discussed in conjunction with parasitic effects, external circuit conditions and doping profiles.Ultra-high-speed switching of less than 10 ps has been shown to be attainable by scaling the device pattern dimensions down to 1 μm order of magnitude.     

Most digital logic circuits in silicon films deposited on sapphire substrates

Details are given of the construction and performance of MOS transistors, logic elements and digital integrated circuits fabricated in silicon layers grown on sapphire substrates and processed on a p-channel enhancement MOST process. P-channel enhancement MOSTs with parameters similar to those of bulk silicon MOSTs, linear resistors with a high sheet resistivity and non-linear resistors are obtained. The use of non-linear resistors is shown to give static logic circuits with operating speeds 2–4 times faster than linear resistors. In addition node capacitance is reduced, the thick oxide MOST is eliminated and dielectric isolation between devices is obtained. Experimental and computer simulated results are given for the performance of a range of logic elements and circuits.