Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

This paper presents a novel approach for implementing ultra-low-power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (subthreshold) regime. Minimum size pMOS transistors with shorted drain-substrate contacts are used as gate-controlled, very high resistivity load devices. Based on the proposed approach, the power consumption and the operation frequency of logic circuits can be scaled down linearly by changing the tail bias current of SCL gates over a very wide range spanning several orders of magnitude, which is not achievable in subthreshold CMOS circuits. Measurements in conventional 0.18 m CMOS technology show that the tail bias current of each gate can be set as low as 10 pA, with a supply voltage of 300 mV, resulting in a power-delay product of less than 1 fJ. Fundamental circuits such as ring oscillators and frequency dividers, as well as more complex digital blocks such as parallel multipliers designed by using the STSCL topology have been experimentally characterized.     

Analysis of High-Speed GaAs Source-Coupled FET Logic Circuits

A source-coupled FET logic (SCFL) circuit is proposed for gigabit rate digital signaf processing. FET threshold voltage tolerance in the SCFL circuit and the SCFL circnit performance are presented. The speed of the SCFL gate depends on the operating region of the FET. For high-speed operation, FET's drain-to-source voltage fdgher than a pinchoff voltage has to be suppfied. The SCFL gate, which is composed of 1.5-pm gate-length FET's, showsthat the minimum propagation time is predicted to be 25 ps/gate. Mhimum rise time and fall time are expected to be S4 ps and 51 ps, respectively. Maximum RZ data rate is expected to be 5.6 Gb/s. The SCFL circnit is applicablefor high-speed dlgitaf sigmd processing.     

边缘注入对H型栅SOI pMOSFETs亚阈值泄漏电流的影响

就不同边缘注入剂量对H型栅SOI pMOSFETs亚阈值泄漏电流的影响进行了研究。实验结果表明不足的边缘注入将会产生边缘背栅寄生晶体管,并且在高的背栅压下会产生明显的泄漏电流。分析表明尽管H型栅结构的器件在源和漏之间没有直接的边缘泄漏通路,但是在有源扩展区部分,由于LOCOS技术引起的硅膜减薄和剂量损失仍就促使了边缘背栅阈值电压的降低。     

Independent-Double-Gate FinFET SRAM for Leakage Current Reduction

An independent-double-gate (IDG) fin-type MOSFET (FinFET) SRAM has been successfully fabricated with considerable leakage current reduction. The new SRAM consists of IDG-FinFETs which have flexible $V_{rm th}$ controllability. The IDG-FinFET with a TiN metal gate is fabricated by a newly developed gate-separation etching process. By appropriately controlling the $V_{rm th}$ of the IDG-FinFET, we have successfully demonstrated the reduction of the leakage current and power consumption of the SRAM circuitry.      

纳米级CMOS电路的漏电流及其降低技术

随着CMOS工艺的进一步发展,漏电流在深亚微米CMOS电路的功耗中变得越来越重要.因此,分析和建模漏电流的各种不同组成部分对降低漏电流功耗非常重要,特别是在低功耗应用中.本文分析了纳米级CMOS电路的各种漏电流组成机制并提出了相应的降低技术.     

Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating

The exponential increase in leakage power due to technology scaling has made power gating an attractive design choice for low-power applications. In this paper, we explore this design style in large combinational circuit blocks and latch-to-latch datapaths and introduce a novel power gating approach to yield an improved power-performance tradeoff. We first present a multiple sleep mode power gating technique where each mode represents a different point in the wake-up overhead versus leakage savings design space. We show that the high wake-up latency and wake-up power penalty of traditional power gating limits its application to large stretches of inactivity. The multiple-mode feature allows a processor to enter power saving modes more frequently, hence, resulting in enhanced leakage savings. We apply the multimode power gating technique to datapaths where the degree of applied power gating becomes progressively stronger (harder) along the datapath. This configuration allows us to further balance wake-up overhead with leakage savings by exploiting the fact that logic circuits deep in the datapath have higher wakeup margin and hence can be strongly gated. Simulations show that multiple sleep mode capability provides an extra 17% reduction in overall leakage compared to traditional single mode gating. The multiple modes can be designed to allow state-retentive modes. The results on benchmarks show that a single state-retentive mode can reduce leakage by 19% while preserving state of the circuit.     

Nanometer Device Scaling in Subthreshold Logic and SRAM

Subthreshold circuit design is promising for future ultralow-energy sensor applications as well as highly parallel high-performance processing. Device scaling has the potential to increase speed in addition to decreasing both energy and cost in subthreshold circuits. However, no study has yet considered whether device scaling to 45 nm and beyond will be beneficial for subthreshold logic. We investigate the implications of device scaling on subthreshold logic and SRAM and And that the slow scaling of gate-oxide thickness leads to a 60% reduction in I_on/I_off between the 90- and 32-nm device generations. We highlight the effects of this device degradation on noise margins, delay, and energy. We subsequently propose an alternative scaling strategy and demonstrate significant improvements in noise margins, delay, and energy in sub-V_th circuits. Using both optimized and unoptimized subthreshold device models, we explore the robustness of scaled subthreshold SRAM. We use a simple variability model and find that even small memories become unstable at advanced technology nodes. However, the simple device optimizations suggested in this paper can be used to improve nominal read noise margins by 64% at the 32-nm node.     

Ultralow-Power Operation in Subthreshold Regimes Applying Clockless Logic

Energy performance requirements are causing designers of next-generation systems to explore approaches to lowest possible power consumption. Subthreshold operation is being examined to stretch low-power circuit designs beyond the normal modes of operation, with the potential for large energy savings. Some of the challenges to be overcome, like 10–100$times$ performance penalties, are being addressed by research into parallelism. However, the uncertainty in timing generated by operating in subthreshold represents a major challenge to overcome. In this paper, first, we will introduce some background information on digital logic subthreshold operation, then provide some background on clockless logic design approaches giving a brief overview of some of the characteristics of the different design styles and focusing on NULL convention logic. Next, we will examine the application of that clockless logic approach to a military system, reviewing the background of the experiment, factors considered in the comparison, and then summarizing the results of the comparisons. Finally, an overview of additional research and development that will be needed to make the technique available to subthreshold designers is presented.      

Power Reduction of Asynchronous Logic Circuits Using Activity Detection

Asynchronous circuits are well known for their benefits in terms of dynamic power savings because asynchronous logic does not switch when inactive. Nevertheless, in deep-submicron technologies, leakage currents have become an increasing issue, and thus, asynchronous circuits need to focus on static-power-consumption reduction. In this paper, we propose an innovative way to detect incoming asynchronous activity. Associated to an automatic power regulation, it efficiently reduces the supply voltage and, thus, both energy per operation and leakage currents. The proposed technique has been applied to an asynchronous network-on-chip node and successfully implemented in an ST Microelectronics CMOS 65-nm technology.      

Interests and Limitations of Technology Scaling for Subthreshold Logic

Subthreshold logic is an efficient technique to achieve ultralow energy per operation for low-to-medium throughput applications. In this paper, the interests and limitations of technology scaling for subthreshold logic are investigated from 0.25 mum to 32 nm nodes. Scaling to 90/65 nm nodes is shown to be highly desirable for medium-throughput applications (1-10 MHz) due to great dynamic energy reduction. However, this interest is limited at 45/32 nm nodes by high static energy due to degraded subthreshold swing and delay variability. Moreover, for low-throughput applications (10-100 kHz), this limitation is worsened by the increase of minimum supply voltage to achieve sufficient functional yield, which results in bad energy efficiency starting at 0.13 mum node. Upsizing the channel length is proposed as a straightforward circuit-level technique to efficiently mitigate these effects. At 32 nm node, this technique reduces energy per operation by 60% at medium throughput and by two orders of magnitude at low throughput.     

Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits

Power gating has been widely used to reduce subthreshold leakage. However, the efficiency of power gating degrades very fast with technology scaling, which we demonstrate by experiment. This is due to the gate leakage of circuits specific to power gating, such as storage elements and output interface circuits with a data-retention capability. A new scheme called supply switching with ground collapse is proposed to control both gate and subthreshold leakage in nanometer-scale CMOS circuits. Compared to power gating, the leakage is cut by a factor of 6.3 with 65-nm and 8.6 with 45-nm technology. Various issues in implementing the proposed scheme using standard-cell elements are addressed, from register transfer level to layout. These include the choice of standby supply voltage with circuits that support it, a power network architecture for designs based on standard-cell elements, a current switch design methodology, several circuit elements specific to the proposed scheme, and the design flow that encompasses all the components. The proposed design flow is demonstrated on a commercial design with 90-nm technology, and the leakage saving by a factor of 32 is observed with 3% and 6% of increase in area and wirelength, respectively.     

GaN HFET中的亚阈值电流和穿通

通过自洽求解二维泊松方程和薛定谔方程发现栅-漏间隙中的强场峰两侧的异质结能带产生巨大畸变,使部分二维电子气不能通过强场峰而形成局域电子气。从电子气补偿效应出发研究了外沟道夹断前后的沟道电阻变化。研究了从外沟道渗透到内沟道的电场梯度和缓冲层沟道阱,发现了新的电场梯度引起的能带下弯(Electric field gradient induced band bowing,EFGIBB)效应。从漏电压引起的电势下降(Drain-induced barrier lowering,DIBL)和EFGIBB两效应出发建立起新的穿通阱模型,由此解释了实验中观察到的各类阈值电压负移、亚阈值电流和穿通等沟道夹断以后的行为,发现了由强负栅压引起的新穿通现象。最后讨论了新穿通行为对器件性能的影响,探索优化设计器件结构,改善器件性能的新途径。     

Automatic Gate Biasing of an SCCMOS Power Switch Achieving Maximum Leakage Reduction and Lowering Leakage Current Variability

Power switch transistors are very effective in cutting the leakage currents of digital circuits in a deep-freeze mode, by de-supplying unused blocks. Among existing power switch transistors, Super Cut-off CMOS (SCCMOS) is the most suited to a low supply voltage environment since it uses a low threshold voltage transistor. This power switch type achieves good leakage reduction results, provided that an optimal voltage is applied on its gate in order to maximize the leakage gain. This optimal voltage value, depending on the operating conditions (process, voltage, temperature), cannot be determined at the design level. A polarization circuit, that automatically finds the optimal bias voltage whatever the environment conditions, was therefore designed and fabricated. This circuit, made in Bulk 65 nm technology, achieves more than two decades leakage current reduction at the power switch level, for a power dissipation overhead of 45 nW at ambient temperature. A very simple scheme is also presented to alleviate the voltage stress applied on the dielectric in case of an ageing of the latter, increasing its time-to-breakdown by several orders of magnitude.     

Junctionless MOS-Transistor with a Low Subthreshold Current

Russian Microelectronics - The junctionless MOS-transistors (junctionless MOSFET) have a number of advantages over conventional transistors in terms of the simplicity of design, manufacturing...     

Sleepy Stack Leakage Reduction

Leakage power consumption of current CMOS technology is already a great challenge. International Technology Roadmap for Semiconductors projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. Leakage is a serious problem particularly for CMOS circuits in nanoscale technology. We propose a novel ultra-low leakage CMOS circuit structure which we call "sleepy stack". Unlike many other previous approaches, sleepy stack can retain logic state during sleep mode while achieving ultra-low leakage power consumption. We apply the sleepy stack to generic logic circuits. Although the sleepy stack incurs some delay and area overhead, the sleepy stack technique achieves the lowest leakage power consumption among known state-saving leakage reduction techniques, thus, providing circuit designers with new choices to handle the leakage power problem     

对称三材料双栅应变硅MOSFET亚阈值电流与亚阈值斜率解析模型

基于泊松方程和边界条件,推导了对称三材料双栅应变硅金属氧化物半导体场效应晶体管（MOSFET：metal oxide semiconductor field effect transistor）的表面势解析解.利用扩散-漂移理论,在亚阈值区电流密度方程的基础上,提出了亚阈值电流与亚阈值斜率二维解析模型.分析了沟道长度、功函数差、弛豫SiGe层的Ge组份、栅介质层的介电常数、应变硅沟道层厚度、栅介质高k层厚度和沟道掺杂浓度等参数对亚阈值性能的影响,并对亚阈值性能改进进行了分析研究.研究结果为优化器件参数提供了有意义的指导.模型解析结果与DESSIS仿真结果吻合较好.     

CdZnTe Radiation Detectors with HgTe/HgCdTe Superlattice Contacts for Leakage Current Reduction

CdZnTe-based heterojunction p?Ci?Cn or M?C???Cn detectors using HgTe/HgCdTe superlattice contacts are modeled and designed to reduce leakage currents under high electric fields and thereby improve x-ray and ??-ray detector performance. The employment of an n-type HgTe/HgCdTe superlattice as a contact layer can theoretically result in significantly less leakage current compared with a contact layer using either bulk semiconductor or metal contacts. The benefits arise from the ability to design HgTe/HgCdTe superlattices to have large carrier effective masses in the electric field direction, which results in low carrier velocities. Nevertheless the density of states is lower than that of a comparable bulk semiconductor, which results in low carrier concentrations.     

Leakage Current Reduction Techniques for 7T SRAM Cell in 45 nm Technology

In this paper the impact of gate leakage on 7T static random access memory (SRAM) is described and three techniques for reducing gate leakage currents and sub threshold leakage currents are examined. In first technique, the supply voltage is decreased. In the second techniques the voltage of the ground node is increased. While in third technique the effective voltage across SRAM cell Vd = 0.348V and Vs = 0.234V are observed. In all the techniques the effective voltage across SRAM cell is decreased in stand-by mode using a dynamic self controllable voltage level (SVL) switch. Simulation results based on cadence tool for 45 nm technology show that the techniques in which supply voltage level is reduced is more efficient in reducing gate leakage than the one in which ground node voltage is increased. Result obtained show that 437 FA reductions in the leakage currents of 7T SRAM can be achieved.