适于器件及电路分析的全耗尽短沟道LDD／LDSSOI MOSFET器件模型

本文系统描述了全耗尽短沟道ＬＤＤ／ＬＤＳＳＯＩＭＯＳＦＥＴ器件模型的电压电压特性。该模型扩展了我们原有的薄膜全耗尽ＳＯＩＭＯＳＦＥＴ模型，文中着重分析了器件进入饱和区后出现的沟道长度调制效应，及由于ＬＤＤ／ＬＤＳ区的存在对本征ＭＯＳ器件电流特性的影响。     

包含自加热效应的短沟道SOIMOSFET直流模型

ＳＯＩＭＯＳＦＥＴ中存在着严重的自加热效应,对其直流特性有较大的影响。给出准确的自加热效应模型是精确模拟ＳＯＩＭＯＳＦＥＴ直流特性的基础。文中通过对自加热效应的分析,建立了ＳＯＩＭＯＳＦＥＴ的自加热效应模型,在此基础上给出了一个包含自加热效应的短沟道ＳＯＩＭＯＳＦＥＴ直流模型,并对该模型进行了验证。     

深亚微米MOSFET二维数值模拟的若干结果

对溶亚微米器件，由于工作电压下降，要求重新确定ＬＤＤ和常规ＭＯＳＦＥＴ在ＶＬＳＩ中的作用。本文从基本器件数理方程发出，对深亚微米常规及ＬＤＤ ＭＯＳＦＥＴ的器件特性、热载流子效应及短沟道效应进行了二维稳态数值模拟，指出了常规和ＬＤＤ ＭＯＳＦＥＴ各自的局限性，明确了在深亚微米ＶＬＳＩ中，ＬＤＤ仍然起主要作用。     

EEPROM单元结构的变革及发展方向

扼要阐述了电可擦除可编程只读存储器（ＥＥＰＲＯＭ）发展史上的各种结构如ＦＡＭＯＳ、ＭＮＯＳ、ＳＩＭＯＳ、ＤＩＦＭＯＳ、ＦＥＴＭＯＳ（ＦＬＯＴＯＸ）等，比较了它们的优缺点，着重论述了ＥＥＰＲＯＭ结构今后的变革方向。     

自对准硅化物SOI／CMOS技术研究

在ＳＯＩ／ＣＭＯＳ电路制作中引入了自对准钴硅化物（ＳＡＬＩＣＩＤＥ）技术，研究了ＳＡＬＩＣＩＤＥ工艺对ＳＯＩ／ＭＯＳＦＥＴ单管特性和ＳＯＩ／ＣＭＯＳ电路速度性能的影响。实验表明，ＳＡＬＩＣＩＤＥ技术能有效地减小ＭＯＳＦＥＴ栅、源、漏电极的寄生接触电阻和薄层电阻，改善单管的输出特性，降低ＳＯＩ／ＣＭＯＳ环振电路门延迟时间，提高ＳＯＩ／ＣＭＯＳ电路的速度特性。     

自对准硅化物CMOS／SOI技术研究

在ＣＭＯＳ／ＳＩＭＯＸＳＯＩ电路制作中引入了自对准钴（Ｃｏ）硅化物（ＳＡＬＩＣＩＤＥ）技术，研究了ＳＡＬＩＣＩＤＥ工艺对ＳＯＩＭＯＳＦＥＴ单管特性和ＣＭＯＳ／ＳＯＩ电路速度性能的影响．实验表明，采用ＳＡＬＩＣＩＤＥ技术能有效地减小ＭＯＳＦＥＴ栅、源、漏电极的寄生接触电阻和方块电阻，改善单管的输出特性，降低ＣＭＯＳ／ＳＯＩ环振电路门延迟时间，提高ＣＭＯＳ／ＳＯＩ电路的速度特性．     

SOI LDD MOSFET的栅电流的模拟

本文介绍一种采用载流子总量方法分析ＳＯＩ ＭＯＳＦＥＴ器件特性及热载流子效应的数值模型。使用专用模拟程序ＬＡＤＥＳ７联解器件内部二维泊松方程、电子和空穴的连续性方案。ＬＡＤＥＳ７可用于设计和预测不同工艺条件、几何结构对器件性能的影响。该模型直接将端点电流、端点电压与内部载流子的输运过程联系在一起，可准确地模拟ＳＯＩ ＭＯＳＦＥＴ器件的特性并给出清晰的内部物理图象。本文给出了ＬＡＤＥＳ７软件模拟的部     

CMOS／SOI电路模拟与参数提取

ＳＯＩ－ＭＯＳＦＥＴ主要模型参数得一致的提取，因而该模型嵌入ＳＰＩＣＥ后能保证ＣＭＯＳ／ＳＯＩ电路的正确模拟工作，从ＣＭＯＳ／ＳＯＩ器件和环振电路的模拟结果和实验结果看，两者符合得较好，说明我们所采用的ＳＯＩ ＭＯＳＦＥＴ器件模型及其参数提取都是成功的。     

极薄SOI MOSFET的2维解析模型

极薄ＳＯＩＭＯＳＦＥＴ的２维解析模型＝Ｔｗｏ－ｄｉｍｅｎｓｉｏｎａｌａｎａｌｙｔｉｃｍｏｄｅｌｉｎｇｏｆｖｅｒｙｔｈｉｎＳＯＩＭＯＳＦＥＴ＇ｓ／［刊，英］／Ｊａｓｏｎ，Ｃ．Ｓ…∥ＩＥＥＥＴｒａｎｓ．ＥｌｅｃｔｒｏｎＤｅｖ－１９９０．３７（９）．－１９...     

THE OUTPUT OPTICAL FIELD INTENSITY DISTRIBUTION FORMED BY AN OPTICAL FIBER END

ＴＨＥＯＵＴＰＵＴＯＰＴＩＣＡＬＦＩＥＬＤＩＮＴＥＮＳＩＴＹＤＩＳＴＲＩＢＵＴＩＯＮＦＯＲＭＥＤＢＹＡＮＯＰＴＩＣＡＬＦＩＢＥＲＥＮＤ￥ＹＵＡＮＬｉ－Ｂｏ（Ｄｅｐａｒｔｍｅｎｔｏｆｐｈｙｓｉｃｓ，ＨａｒｂｉｎＥｎｇｉｎｅｅｒｉｎｇＵｎｉｖｅｒｓｉｔｙ...     

A numerical analysis of avalanche breakdown in short-channel MOSFETs

Recently, the electrical characteristics for the short channel MOSFETs (Metal-Oxide-Semiconductor field effect transistor) have become important because of the increasing density of LSIs (Large Scale Integrated Circuits). One of the methods to understand the characteristics of the short channel MOSFETs is the two-dimensional analysis of the MOSFETs, and many studies about threshold voltage and other items have been made by using the two-dimensional method. In this paper, the drain breakdown characteristics for the short channel MOSFETs are calculated by the two-dimensional analysis method. Consequently, one of the phenomena for the short channel MOSFETs, that the breakdown voltage decreases with increase in gate voltage, is reduced to the difference of the electric field strength distribution from that of the long channel MOSFETs. This variation of the electric field distribution is caused by the strong influence of the electric field from the drain upon the considerable region in the substrate of the short channel MOSFETs.     

Three-dimensional analytical subthreshold models for bulk MOSFETs

Three-dimensional device-physics-based analytical models are developed for subthreshold conduction in uniformly doped small geometry (i.e., simultaneously short channel and narrow width) bulk MOSFETs, for various isolation schemes. Inverse-narrow width effects, where the threshold voltage decreases with decreasing channel width, are predicted by the model for trench isolated MOSFETs. For LOGOS isolated MOSFETs, conventional narrow width effects, where the threshold voltage increases due to decreasing channel width, are predicted. The narrow width effects are found to be comparable to the short channel effects in the absence of significant applied drain biases. However, for larger drain biases, the short channel effects outweigh the narrow width effects due to the weaker potential perturbation at the device width edges compared to the drain end. Unlike the threshold voltage, the subthreshold swing of the device is found to increase with reduced device dimensions regardless of the isolation scheme since both conventional and inverse narrow width effects result in weaker control of the surface potential by the gate     

An accurate two-dimensional CAD-oriented model of retrograde doped MOSFETs for improved short channel performance

An analytical CAD-oriented model for short channel threshold voltage of retrograde doped MOSFETs is developed. The model is extended to evaluate the drain induced barrier lowering parameter (R) and gradient of threshold voltage. The dependence of short channel threshold voltage and R on thickness of lightly doped layer (d) has also been analyzed in detail. It is shown that a retrograde doping profile reduces short channel effects to a considerable extent. A technique is developed to optimize the device parameters for minimizing short channel effects. The results so obtained are in close proximity with published data.     

A unified analytical model for drain-induced barrier lowering and drain-induced high electric field in a short-channel MOSFET

Using the well known El-Mansy-Ko method, a simple solution of the two dimensional Poisson equation is derived at the SiSiO₂ interface for the region bounded by the source and the drain. The solution is valid for long channel as well as short channel MOSFETs. The effect of variable values of the depletion depth is incorporated using the WKB approximation. The solution yields a new model of the subthreshold voltage of a short channel MOSFET. The solution also provides mathematical justification of the intuitive assumptions made by Hsu, Muller and Hu in their paper on punch through currents in short channel MOSFETs. Since the single solution gives both the drain induced high field, DIHF, and the drain induced barrier lowering, DIBL, it also yields an analytical relation between them. The DIBL increases approximately expnentially as E_max decreases. The results obtained from this model are in agreement with the numerical simulations and are consistent with the known experimental results.     

Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs

A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOSFET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO (Atlas) tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of symmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2.     

新型槽栅MOSFETs的特性

采用SIVALCO软件对槽栅与平面器件进行了仿真对比分析,结果表明槽栅器件能够有效地抑制短沟道及热载流子效应,而拐角效应是槽栅器件优于平面器件特性更加稳定的原因.对自对准工艺下成功投片所得沟道长度为140nm的槽栅器件进行测量,结果有力地证明了槽栅器件较平面器件的优越性.     

Short channel epi-MOSFET model

We show how threshold voltages and the electric field perpendicular to a channel are controlled by varying the thickness of the epi-layer in long epitaxial channel MOSFET devices (epi-MOSFETs). Using our proposal of a two-region polynomial potential distribution and a universal boundary condition that effectively expresses the variation of depletion width along a channel, we calculated the two-dimensional (2-D) potential distribution. We also derived a threshold voltage model for short channel epi-MOSFETs. Our model reproduces the numerical data of sub-0.1-/spl mu/m gate length devices, and predicts that the short channel immunity of these devices is not as good as predicted by the previous model. However, their performance is superior to that of double-gate SOI MOSFETs.     

Threshold Voltage model for mesa-isolated small geometry fully depleted SOI MOSFETs based on analytical solution of 3-D Poisson's equation

A threshold voltage model for mesa-isolated fully depleted silicon-on-insulator (FDSOI) MOSFETs, based on the analytical solution of three-dimensional (3-D) Poisson's equation is presented for the first time in this paper. The separation of variables technique is used to solve the 3-D Poisson's equation analytically with appropriate boundary conditions. Simple and accurate analytical expressions for the threshold voltage of the front and the back gate are derived. The model is able to predict short channel as well as narrow width effects in mesa-isolated FDSOI MOSFETs. The model is validated by comparing with the experimental results as well as with the numerical results available in the literature.     

Two-dimensional threshold voltage analytical model of DMG strained-silicon-on-insulator MOSFETs

For the first time,a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator(DMG SSOI) MOSFETs is developed.We investigate the improved short channel effect(SCE),hot carrier effect(HCE),drain-induced barrier-lowering(DIBL) and carrier transport efficiency for the novel structure MOSFET.The analytical model takes into account the effects of different metal gate lengths,work functions,the drain ...     

A new short channel MOSFET structure (UMOST)

A new MOSFET structure with a trapezoidal U-shaped channel defined by anisotropic etching is described. The structure results in very short channel devices almost free of short channel effects and achieves higher speed without the use of submicron photolithography. A simplified theory for the structure is presented and compared with experimental results obtained on 1–10 μm channel length devices. This structure may prove useful in the study of conduction in short channel MOSFETs without introducing the complicating two dimensional short channel effects.