超薄氧化层的电击穿特性

本文在测试分析N 理层—隧道氧化层一多晶硅电容（N OP电容）、P衬底一隧道氧化层一多晶硅电容（POP电容）和EEPROM单元隧道氧化层电容（TOP电容）的I－V特性、I－t特性、V－t特性的基础上,对隧道氧化层的击穿特性进行了理论分析,并提出了提高隧道氧化层可靠性的具体措施。     

高场应力对隧道氧化层电特性的影响

详细研究了Ｎ＾＋埋层－隧道氧化层－多晶硅电容和Ｐ型衬底－隧道氧化层－多晶硅电容在高场应力下的高频Ｃ－Ｖ特性和Ｉ－Ｖ特性的漂移,以及两种电容在隧道氧化层中陷阱电荷的产生现象。     

基于SiC基底的Y2O3/Al2O3堆栈MOS 电容的特性研究

通过在n型碳化硅(SiC)晶圆上用物理气相沉积法(PVD)和原子层沉积法(ALD)分别沉积 Y2O3介质和Al2O3，形成金属/Al2O3/Y2O3/SiC高k介质堆栈结构MOS电容，X射线光电子能谱(XPS)分析研究Al2O3/Y2O3堆栈结构氧化层介质之间以及氧化层与SiC晶圆之间的相互扩散和反应关系，研究不同金属电极MOS电容的C-V特性，Ni电极MOS电容具有良好的稳定性，对介质层的相对介电常数影响最小，Mg电极MOS电容的理想平带电压最小，同时氧化层陷阱密度最小，随着C-V测试频率的降低，氧化层电容Cox逐渐增加Al2O3/Y2O3介质层的相对介电常数逐渐增大，等效氧化层厚度(EOT)减小，平带电容电压减小。     

PCB布线中的过孔和电容效应分析和结构优化

在多层PCB布线中,过孔和电容是常见的不连续结构。信号线在不同平面间转换传输路径时,过孔与回流层之间的寄生电容与寄生电感将引起信号完整性的相关问题;而常用的传输线上的AC耦合电容等,引入了阻抗突变的结构,由此带来了反射等相关问题。通过对多层PCB上的过孔进行建模仿真,研究不同变量对过孔性能的影响趋势,以协助信号完整性问题的分析;通过对电容阻抗突变处进行不同形式的补偿,仿真和测试结果相验证,得到提高信号传输质量的解决方案。     

硅在高压低温水汽氧化中缺陷的形成

通过大量实验,研究了硅片在700℃和20个大气压的水汽中加速氧化后的完整性。全部实验都是采用直径为3吋的片子。对所研究的所有不同氧化层厚度(直到5μm厚),(100)和(111)取向的n型和p型硅的高压水汽氧化都抑制了氧化感生的堆垛层错。将一部分片子在一个标准大气压下进行水汽氧化,使其产生堆垛层错,接着又在高压下进行水汽氧化,以便研究这些堆垛层错的特性。结果表明,高压水汽氧化后,堆垛层错的长度有某种程度的收缩,其收缩量小于仅根据硅的消耗量所预计的值。对高压水汽氧化的样品进行了电容瞬态测量,并与一个大气压下更高温度处理后的片子进行了比较,发现高压水汽氧化后的缺陷态密度与预氧化条件下得到的结果几乎相同。     

采用轴对称二维有限元法提取过孔分布电容

采用简便的两维轴对称有限元法分析了四层印制电路板的过孔电容。将极坐标形式的拉普拉斯方程变换成直角坐标形式,避免了复杂的椭圆积分。将过孔的电容分层处理,分析了过孔的高度、半径、焊盘半径等参数对过孔电容的影响。与有限元分析软件ANSYS进行了对比,计算结果基本一致。此方法可用于任意层复杂印制电路板过孔电容的提取,所得结论有助于过孔的等效电路建模以及高速PCB的信号完整性分析。     

集成电路氧化层失效定位技术研究

介绍了一种针对集成电路氧化层失效的定位和分析技术。采用光发射显微镜、光致电阻变化技术,对比出电路中不同的发光机构或电阻变化点。结合电路故障假设法和版图分析,对氧化层失效位置进行定位。最终,采用制样和物理分析方法,找到失效原因。案例分析表明,该方法精确、快速,可应用于CMOS集成电路的栅氧化层、双极集成电路的MOS电容氧化层、GaAs集成电路的MIM电容的失效定位,减少了后续FIB或RIE等物理分析方法的工作量,提高了失效分析的成功率。     

高温恒定电场栅氧化层TDDB寿命测试方法研究

介绍了薄栅氧化层TDDB可靠性评价的高温恒定电场试验方法,并完成了E模型的参数提取,同时以MOS电容栅电流Ig为失效判据。对某工艺的MOS电容栅氧化层TDDB寿命进行了评价。该试验方法解决了在高温条件下对工作器件进行可靠性评价的问题,方法简便可靠,适用于亚微米和深亚微米工艺线的可靠性评价。     

二次热处理的SrTiO3压敏陶瓷电性能的研究

采用逐层研磨及电测量的方法,对800~1050℃不同温度下,热处理的SrTiO3陶瓷电容–压敏元件的表面氧化层进行了研究。结果表明:该类元件存在明显的表面氧化层结构,且随着热处理温度升高,表面氧化层厚度增大,800~1000℃不同温度热处理的样品,其表面氧化层厚度为26~107μm;表面氧化层内扩散氧的浓度和晶界势垒的高度是由表及里逐渐减小的。     

一个超薄氧化物nMOSFET器件的直接隧穿电流经验公式

建立了一个直接隧穿电流的经验公式.将氧化层厚度作为可调参数,用这个经验公式可以很好地拟合超薄氧化物nMOSFET器件的直接隧穿电流.在拟合中所得到的氧化层厚度比用量子力学电压-电容方法模拟得到的氧化层厚度小,其偏差在0.3nm范围内.     

Mercury-probe characterisation of soft breakdown: effect of oxide thickness and measurement set-up

The breakdown of 4–7 run gate oxides is investigated using fast-feedback Hg-probe measurements to perform Exponentially Ramped Current Stress (ERCS) tests. Soft breakdown is detected in oxides thinner than 5 nm. However, it is found that the detection of soft-breakdown during ERCS test depends on the measurement set-up. In particular, it can be completely suppressed by reducing the gate oxide capacitor area. The consequences of this result for correct routine assessment of gate oxide integrity in microelectronic manufacturing are discussed.     

An electrical study of SIMOX material by a quick-turn-around approach

Circuits built on silicon-on-insulator (SOI) substrates, have different requirements for material quality, depending on the intended application. Thus, the need exists for a detailed characterization of the electrical properties of the silicon and buried oxide layers. In this paper, we study the effects of processing on the electrical characteristics of SOI wafers formed by the implantation of oxygen (SIMOX). To facilitate this investigation, we developed a quick-turn-around (QT) approach, based on C-V and C-t measurements on a capacitor formed with the buried oxide as the capacitor dielectric. A simple process is used to isolate silicon islands in the film layer, thus delineating the capacitor. The measurements allow one to determine the fixed oxide charge and interface trap densities of both buried oxide interfaces, and the minority carrier generation time of both the film and substrate. The QT approach is used to study the effects of changing the post-implant anneal time and temperature, and of using a screen oxide during the oxygen implant.     

Study on composition in niobium anode

Niobium capacitor uses electrolytic Nb205 as dielectric layer formed on surface of porous niobium anode through electrolytic reaction. Analysis of Scanning Electronics Microscope (SEM) combined with X-ray Photoemission Spectrum(XPS) shows that the formed niobium oxidedielectric consists of not only Nb2O5, but also two kinds of low valence niobium NbO2 and NbO oxide. When using different electrolytic reaction conditions, different valence niobium oxide shows different relative content. The fact provides an important basis for analyzing and improving performances of niobium capacitor.     

Polysilicon capacitor failure during rapid thermal processing

Rapid thermal-processing-induced polysilicon capacitor failure is investigated. Polysilicon-SiO2-Si capacitors fail at the perimeter upon heating to temperatures in excess of 1050°C for a few seconds in vacuum or argon. Shorting occurs when the silicon grains deform due to surface energy-driven diffusion and extend over etch-damaged oxide surrounding the capacitor. The presence of oxygen or nitrogen during, or regrowth of the damaged oxide prior to, rapid thermal processing substantially reduces the failure rate.     

A model for analyzing the interface properties of asemiconductor-insulator-semiconductor structure. I. Capacitance andconductance techniques

A model is presented for analyzing the interface properties of a semiconductor-insulator-semiconductor (SIS) capacitor structure. By introducing a coupling factor, conventional metal-oxide-semiconductor (MOS) capacitor theory is extended to analyze the interface properties of the film/buried-oxide/substrate interfaces of a silicon-on-insulator (SOI) material. This model was used to determine parameters such as doping concentration, buried oxide thickness, fixed oxide charge, and interface trap density from the SIMOX (separation by implantation of oxygen) based SIS capacitors     

基于ANSYS 的DDR4 SDRAM 信号完整性仿真方法研究

半导体技术快速发展,双倍数据速率同步动态随机存取存储器(Double Data Rata Synchronous Dynamic Random Access Memory, DDR SDRAM)的信号完整性问题已成为设计难点。文中提出了一种基于ANSYS 软 件和IBIS 5. 0 模型的DDR4 SDRAM 信号完整性仿真方法。利用IBIS 5. 0 模型中增加的复合电流(Composite Current) 、同步开关输出电流等数据,对DDR4 SDRAM 高速电路板的信号完整性进行更准确的仿真分析。仿真结果 表明:高速信号在经过印制板走线和器件封装后,信号摆幅和眼图都有明显恶化;在仿真电路的电源上增加去耦 电容后,信号抖动和收发端同步开关噪声(Synchronous Switching Noise, SSN)都得到明显改善;在不加去耦电容的 情况下,将输入信号由PRBS 码换成DBI 信号,接收端的同步开关噪声有所改善,器件功耗可以降为原来的一半。     

Analysis of band-to-band tunneling leakage current intrench-capacitor DRAM cells

Evidence demonstrating that the band-to-band tunneling leakage current occurs mainly at the edge of the self-aligned isolation rather than the trench upper corners is presented. Moreover, the leakage current increases drastically with the decrease of capacitor oxide thickness. It is shown that the leakage current limits the thickness of capacitor oxide to more than 80 Å even if the operation voltage is reduced to 3.3 V from 5 V     

Correlation between oxide breakdown and defects in SiC wafers

A correlation between gate oxide breakdown in metal oxide semiconductor (MOS) capacitor structures and structural defects in SiC wafers is reported. The oxide breakdown under high applied fields, in the accumulation regime of the MOS capacitor structure, is observed to occur at locations corresponding to the edge of bulk structural defects in the SiC wafer such as polytype inclusions, regions of crystallographic misorientation, or different doping concentration. Breakdown measurements on more than 50 different MOS structures did not indicate any failure of the oxide exactly above a micropipe. The scatter in the oxide breakdown field across a 10 mm × 10 mm square area was about 50%, and the highest breakdown field obtained was close to 8 MV/cm.