横向高压器件LDMOS与LIGBT的特性分析

给出了横向高压器件ＬＤＭＯＳ、ＬＩＧＢＴ以及具有阳极短路结构的ＬＩＧＢＴ的输出特性、开关特性及耐压特性模拟曲线，并对这三种器件的结构和性能进行了较系统的分析与对比。     

空穴注入控制型横向绝缘栅双极晶体管

提出了空穴注入控制型横向绝缘栅双极晶体管（ＣＩ－ＬＩＧＢＴ）,它可以有效地控制高压下阳极区穴穴注入,提高器件的闭锁电压。通过对阳极区反偏ｐ＾＋ｎ＾＋结 穿电压ＢＶＺ、取样电阻ＲＡ和阳极区结深的优化,提高了ＣＩ－ＬＩＧＢＴ的抗闭锁能力,降低了其导通压卫,并获得了初步实验结果。     

带快速复位的光电隔离栅极驱动

光电隔离器（ＰＶＩ）为ＭＯＳＦＥＴ和ＩＧＢＴ提供隔离的栅极驱动。但是，在关断时，ＰＶＩ不能下拉栅极排放栅极电荷。采用一个可编程结晶体管（ＰＵＴ）就可提供很快的栅极下拉，在０．２μｓ内使栅极放电，排放掉高达５Ａ的电流。ＰＵＴ为一四层结构，很像可控硅整流器．但它具有更灵敏的阳极选通。在该应用中，ＰＵＴ栅极由ＰＶＩ驱动，其驱动电压等于或大于保持ＰＵＴ处于阻塞状态时的阳极电压，这样就没有电流流经阳极一阴极通道（图１）。当ＰＶＩ“关断”时，ＰＵＴ的栅极电压下降到低于阳极电压，触发ＰＵＴ并导致阳极－阴极通道…     

阳极短路垂直型IGBT的优化模型

提出了一种阳极短路垂直型ＩＧＢＴ的优化设计模型,阐述了导通压降、关断时间及闭锁电流之间的折衷关系。该模型为阳极短路ＩＧＢＴ的设计提供了一种有效的方法。     

Nb超导量子结中AlOx—Al厚度对其特性的影响

通过阳极氧化电压谱图（ＡＶＳ），Ｉ－Ｖ特性和Ｆｉｓｋｅ台阶电压测量，我们研究了Ｎｂ超导量子结构中ＡｌＯｘ－Ａｌ厚度对其特性的影响。发现ＡＶＳ中ＡｌＯｘ－Ａｌ与Ｎｂ电极之间的界面陡度和Ｉ－Ｖ特性取决于ＡｌＯｘ－Ａｌ厚度，Ｎｂ｜ＡｌＯｘ－Ａｌ｜Ｎｂ结的最小最佳沉积Ａｌ层厚度为７ｎｍ。     

采用多孔氧化硅形成超薄SOI结构的研究

本文采用多孔氧化硅全隔离技术获得了硅膜厚度小于１００ｎｍ、硅岛宽度大于１００μｍ的超薄ＳＯＩ（ＴＦＳＯＩ）结构．用透视电子显微镜剖面分析技术（ＸＴＥＭ）、扩展电阻分析（ＳＲＰ）、喇曼光谱、台阶轮廓仪和击穿电压测量等技术对多孔氧化硅超薄ＳＯＩ结构进行了分析，结果表明其顶层硅膜单晶性好，硅膜和埋层氧化层界面平整．实验表明硅岛的台阶形貌及应力状况取决于阳极化反应条件．在硅膜厚约为８０ｎｍ的ＴＦＳＯＩ材料上制备了ｐ沟ＭＯＳＦＥＴ，输出特性良好．     

自对准结构α—Si：H TFT特性的分析和研究

本文描述了用自对准工艺制备自对准结构的αＳｉ：Ｈ ＴＦＴ。从理论上分析了有源层α－Ｓｉ：Ｈ的厚度对α－Ｓｉ：Ｈ ＴＦＴ特性的影响，据此提出一种新型的双有源层结构的α－Ｓｉ ＴＦＴ。它可以有效地提高自对准αＳｉ：Ｈ ＴＦＴ的开态ＩＯＮ，其通断电流比ＩＯＮ／ＩＯＦＦ＞１０＾５。     

Nb超导量子结中AlO_x－Al厚度对其特性的影响

通过阳极氧化电压谱图（ＡＶＳ）；Ｉ－Ｖ特性和Ｆｉｓｋｅ台阶电压测量，我们研究了Ｎｂ超导量子结构中ＡｌＯｘ－Ａｌ厚度对其特性的影响。发现ＡＶＳ中ＡｌＯｘ－Ａｌ与Ｎｂ电极之间的界面陡度和Ｉ－Ｖ特性取决于ＡｌＯｘ－Ａｌ厚度，Ｎｂ｜Ａ｜Ｏｘ－Ａｌ｜Ｎｂ结的最小最佳沉积Ａｌ层厚度为７ｎｍ。由Ｆｉｓｋｅ台阶电压，ＡＶＳ中的Ａｌ峰和Ｉ－Ｖ特性的畸变，证实了结中Ａｌ／Ｎｂ间由常态Ａｌ而引起的亲近效应的存在，并用ＭｃＭｉｌｌａｎ理论作了讨论。     

自对准结构α－Si：HTFT特性的分析和研究

本文描述了用自对准工艺制各自对准结构的α－Ｓｉ：ＨＴＦＴ。从理论上分析了有源层α－Ｓｉ：Ｈ的厚度对α－Ｓｉ：ＨＴＦＴ特性的影响，据此提出一种新型的双有源层结构的α－ＳｉＴＦＴ。它可以有效地提高自对准α－Ｓｉ：ＨＴＦＴ的开态Ｉ＿（ＯＮ），其通断电流比Ｉ＿（ＯＮ）／Ｉ＿（ＯＦＦ）＞１０￣５。     

与众不同的SKM系列IGBT功率模块

德国西门康公司生产的ＳＫＭ系列ＩＧＢＴ功率模块，不必使用ＲＣＤ吸收电路，并联时能自动均流，开关损耗不随温度正比地产加，ＳＯＡ曲线为矩形，并具有不必负压关断、短路电流自动抑制、正温度特性且没有寿命刹手特点。本文分析了ＳＫＭ系列ＩＧＢＴ功率模块的特点，并与其它型号ＩＧＢＴ进行了比较。     

多孔硅发光机制的分析

从量子力学的基本理论出发讨论了量子限制效应，推导出多孔硅有效禁带宽度增量并用量子限制效应和表面态及其物质在发光中作用的理论解释了ＰＳ光致发光的实验现象。     

Double-polysilicon SiGe HBT architecture with lateral base link

We present an analysis of a modified double-polysilicon SiGe:C HBT module showing a CML ring oscillator gate delay τ_D of 2.5 ps, and f_T/f_max/BV_CEo values of 300 GHz/350 GHz/1.85 V (Fox et al., 2008) [1]. A key feature of the HBT module is a connection of the extrinsic and intrinsic base regions by lateral epitaxial overgrowth, which aims to overcome the limits of the conventional double-polysilicon architecture in simultaneously reducing R_B and C_BC. Potential benefits and barriers of the proposed device structure on the way to higher performance are reviewed with regard to the recently demonstrated performance gain of the classical double-polysilicon approach. The paper addresses technological challenges one is faced when the here presented device structure is scaled to minimum device dimensions.     

大功率硅-硅直接键合静电感应晶闸管的研制

文章提出了用硅-硅直接键合（SDB）工艺替代静电感应晶闸管（SITH）中的二次外延，有效地提高了栅阴极击穿电压，增强了通过栅极正向阻断阳极电压的能力。对键合过程中硅-硅界面进行了研究，提出了提高界面质量的工艺措施；同时，给出了控制栅阴极击穿电压一致性的方法。对采用此方法制成的SITH的I-V特性进行了测量，并给出了实际测试结果。     

创新铸就高质量

该文回顾了质量管理发展的历史,探索了现代企业质量管理中提高产品质量的一种新实践模式,即将6sigma的分析方法与TRIZ的创新理论相结合,彻底地解决矛盾,而不是优化参数,最终达到满意的质量水平。并且通过企业的一个实际案例,来讲解具体的操作办法。     

Improvement of data retention characteristics of OSOSO multi-stacked MIS capacitor for flat panel display technology

The data retention ability in metal–oxide–silicon–oxynitride–silicon (MOSOS) devices can be improved using a thicker tunneling layer and novel multi-stacked oxide–silicon–oxynitride–silicon–oxynitride (OSOSO) structure. The OSOSO devices showed 7 fold increase (53.5%) of data retention after a decade compared to OSO devices (6.71%). The improvement in data retention is attributed to the excellent resistance of the charge retention due to the redistribution of electric field across the multi-stacked layers. The spilt storage layer provided a room for storing more charges in different positions of the layers resulting in ~2–3 times increase in memory window. Hence, the performances of those devices are suitable for data storage application in the system-on-panel (SOP) display.     

Development of metal etch mask by single layer lift-off for silicon nitride photonic crystals

We present a method for fabrication of nanoscale patterns in silicon nitride (SiN) using a hard chrome mask formed by metal liftoff with a negative ebeam resists (maN-2401). This approach enables fabrication of a robust etch mask without the need for exposing large areas of the sample by electron beam lithography. We demonstrate the ability to pattern structures in SiN with feature sizes as small as 50 nm. The fabricated structures exhibit straight sidewalls, excellent etch uniformity, and enable patterning of nanostructures with very high aspect ratios. We use this technique to fabricate two-dimensional photonic crystals in a SiN membrane. The photonic crystals are characterized and shown to have quality factors as high as 1460.     

一种新型硅微陀螺仪闭环驱动方案的研究

研究了一种新的硅微陀螺仪闭环驱动方案,对推挽驱动方式的性能进行了分析,结果表明驱动力矩的频段与噪声信号频段是分离的,因此噪声信号不会影响到驱动效果。在此基础上,利用锁相技术满足正弦自激振荡的相角和增益条件,建立环路的自激振荡,实现了闭环控制。同时在闭环回路中利用正弦自激振荡的相角条件和锁相环的鉴相特性,消除了驱动信号对敏感信号的同频干扰,并抑制了环路中的噪声干扰,明显提高闭环性能。试验结果显示在1小时内交流信号频率和幅度的标准方差分别为0.132 H z和0.258 mV,实现了驱动稳幅稳频的目的,从而使陀螺仪精度和可靠性得到了显著提高。     

A comparative study of micropipe decoration and counting in conductive and semi-insulating silicon carbide wafers

Micropipes are considered to be one of the most serious defects in silicon carbide (SiC) wafers affecting device yield. Developing a method to count and map micropipes accurately has been a challenging task. In this study, the different etching behavior of conductive and semi-insulating wafers in molten potassium oxide (KOH) is compared. Micropipes and closed-core screw dislocations exhibit different morphology after etching and can be easily distinguished with a polishing process. Based on a new sample preparation procedure and a digital imaging technique, a novel method of efficiently and reliably mapping and counting micropipes in both conductive and semi-insulating SiC wafers is developed.     

Epitaxial spinel growth for integrated circuits

This is a report on our investigation of the epitaxial growth of Si-on-spinel-on-Si double-heterostructure integrated circuit material. The spinel epitaxial layers were grown on the Si substrate with an open-tube Al-HCl-MgCl₂-CO₂H₂ VPE system. High electron Hall-mobility and low defect density in the active Si layers were achieved with optimum growth conditions for spinel and silicon. Bipolar transistors, MOS devices and high-voltage bipolar ICs were fabricated in the active Si layers on epitaxially grown spinel.     

温度对碳化硅粉料合成的影响

采用高温合成方法生成了高纯碳化硅(SiC)粉.采用高纯碳(C)粉和硅(Si)粉直接反应,不需外加添加剂,通过控制外部加热使Si和C持续反应.实验结果表明,在相同反应时间条件下,不同加热温度对生成的SiC粉料的粒度和纯度有很大影响.当反应温度从1920℃升高到1966℃时,生成的SiC粉粒度由12.548μm增加到29.259μm.当温度继续升高,SiC粉的粒度逐渐减小.温度高于2000℃时,SiC粉的粒度趋于约20μm.同时,X射线衍射图分析表明,温度高于2000℃时,生成的SiC粉料中C比例会明显增加.