Ni(W)Si/Si肖特基势垒二极管电学特性研究

首次提出在Ni中掺入夹层W的方法来提高NiSi的热稳定性。具有此结构的薄膜,经600~800℃快速热退火后,薄层电阻保持较低值,小于2Ω/。经Raman光谱分析表明,薄膜中只存在NiSi相,而没有NiSi2生成。Ni(W)Si的薄层电阻由低阻转变为高阻的温度在800℃以上,比没有掺W的镍硅化物转变温度的上限提高了100℃。Ni(W)Si/Si肖特基势垒二极管能够经受650~800℃不同温度的快速热退火,肖特基接触特性良好,肖特基势垒高度为0.65 eV,理想因子接近于1。     

深槽Ni(Pt)Si/Si肖特基二极管特性研究

采用15nmNi/1.5nmPt/15nmNi/Si结构在600～850°C范围内经RTP退火的方法形成Ni(Pt)Si薄膜,其薄膜电阻低且均匀一致。比形成较低电阻率的NiSi薄膜的温度提高了150°C。在850°CRTP退火后形成的Ni(Pt)Si/Si肖特基势垒二极管I-V特性很好,其势垒高度ΦB为0.71eV,改善了肖特基二极管的稳定性。实验表明在肖特基二极管中引入深槽结构,可以大幅度地提高其反向击穿电压。在外延层浓度为5E15cm-3时,深槽器件的击穿电压可以达到80V,比保护环器件高约30V。     

Ni(W)Si/Si肖特基势垒二极管电学特性研究

文中首次提出在Ni中掺入夹层W的方法来提高NiSi的热稳定性。具有此结构的薄膜,经600℃～800℃快速热退火后,薄层电阻保持较低值,小于2Ω/□。经Raman光谱分析表明,薄膜中只存在NiSi相,而没有NiSi2生成。Ni(W)Si的薄层电阻由低阻转变为高阻的温度在800℃以上,比没有掺W的镍硅化物的转变温度的上限提高了100℃。Ni(W)Si/Si肖特基势垒二极管能够经受650℃～800℃不同温度的快速热退火,肖特基接触特性良好,肖特基势垒高度为0.65eV,理想因子接近于1。     

Ni(Zr)Si薄膜热稳定性及其肖特基势垒二极管的电学特性

提出在Ni中掺人夹层Zr的方法来提高NiSi的热稳定性.具有此结构的薄膜,600～800℃快速热退火后,薄层电阻保持较低值,小于2Ω/□.经XRD和Raman光谱分析表明,薄膜中只存在低阻NiSi相,而没有高阻NiSi2相生成.Ni(Zr)Si的薄层电阻由低阻转变为高阻的温度在800℃以上,比没有掺Zr的镍硅化物的转变温度上限提高了100℃.Ni(Zr)Si/Si肖特基势垒二极管能够经受650～800℃不同温度的快速热退火,肖特基接触特性良好,肖特基势垒高度为0.63eV,理想因子接近于1.     

Ni(Zr)Si薄膜热稳定性及其肖特基势垒二极管的电学特性

提出在Ni中掺入夹层Zr的方法来提高NiSi的热稳定性．具有此结构的薄膜,600～800℃快速热退火后,薄层电阻保持较低值,小于2Ω/□．经XRD和Raman光谱分析表明,薄膜中只存在低阻NiSi相,而没有高阻NiSi2相生成．Ni(Zr)Si的薄层电阻由低阻转变为高阻的温度在800℃以上,比没有掺Zr的镍硅化物的转变温度上限提高了100℃．Ni(Zr)Si/Si肖特基势垒二极管能够经受650～800℃不同温度的快速热退火,肖特基接触特性良好,肖特基势垒高度为0.63eV,理想因子接近于1．     

一种利用夹层Ta难熔金属提高NiSi薄膜热稳定性的新方法

本文首次给出了一种具有规律性的能用来提高镍硅化物热稳定性的方法.依据此方法,首次摸索出在Ni中掺入夹层金属Ta来提高NiSi硅化物的热稳定性.Ni/Ta/Ni/Si样品经600 ～ 800℃快速热退火后,薄层电阻率保持较小值,约2Ω□.XRD衍射分析结果表明,在600～800℃快速热退火温度下形成的Ni(Ta)S薄膜中...     

VLSI中钛硅化物肖特基接触特性与退火条件

基于 Ti Si2 低电阻率的优点 ,采用 Ti制作肖特基二极管。在 VL SI工艺中实现同时完成钛硅化物欧姆接触和肖特基势垒二极管 (SBD)的制作。文中用 AES等技术研究不同退火工艺形成的 Ti/ Si界面形态和结构 ,寻找完善的工艺设计和退火条件。此外还测量 Al/ Ti N/ Ti/ Si结构的金属硅化物 SBD的有关特性。通过工艺实验确定 VL SI中的钛硅化物最佳的制作工艺条件     

微波肖特基势垒二极管硅化物工艺技术研究

对微波肖特基中、低势垒二极管硅化物的工艺技术进行了研究。用Ｎｉ－Ｓｉ硅化物作中势垒硅化物,用Ｔｉ－Ｓｉ硅化物作低势垒硅化物。通过设计和工艺实验,得到温度、时间、真空度等取佳工艺技术条件。在保持微波肖特基二极管势垒特征的同时,提高了反向电压,增强了它的稳定性和可靠性。     

CoSi_2/n—Si肖特基势垒的形成和特性

本文利用XRD、RBS、AES和四探针等方法研究了不同温度快速热退火后的Co/Si结构薄膜固相反应形成钴硅化物的相序、组份和电学特性。并报道了性能优越的CoSi_2/n-Si肖特基二极管的特性,其势垒高度为0.66eV,理想因子为1.01。     

Al/C60/Cu薄膜结构的电学性质

将C60薄膜沉积在Al上,制成了Al/C60结构的薄膜二极管。对Al/C60结构的肖特基结构与金属-绝缘层-半导体(MIS)结构的电学特性做了研究。Al/C60肖特基结构在偏压±2 V时的整流比为30,而Al/C60的MIS结构在偏压±2 V时整流比为100。在MIS结构中,AlOx的形成起着关键的作用。研究还发现,刚沉积好的薄膜二极管,其整流效应并不理想,在真空中经退火处理后,其性能得到增强。此二极管在空气中无封装情况下表现出高稳定性。     

难熔夹层金属提高NiSi薄膜热稳定性的新思路

首次给出了一种具有规律性的能用来提高镍硅化物热稳定性的方法.依据此方法,摸索出在Ni中分别以夹层金属掺入Pt、Mo、Zr、W金属来提高NiSi硅化物的热稳定性.概括总结了掺人难熔金属M后形成的三元镍硅化物Ni(M)Si热稳定性能.实验结果表明,Ni(M)Si硅化物薄膜四种镍硅化物薄膜有相同的热稳定性.以Ni/W/Ni/...     

Ni- and Co-based silicides for advanced CMOS applications

The scaling behavior of Co, Co–Ni and Ni silicides to sub-40 nm gate length CMOS technologies with sub-100 nm junction depths was evaluated. Limitations were found for Co and Co–Ni alloy silicides, which exhibited an increase in sheet resistance at gate lengths below 40 nm and required high processing temperatures to achieve low junction leakage. Ni silicide was shown, in contrast, to have good scaling behavior, with a decrease in sheet resistance for decreasing gate lengths down to 30 nm, lower diode leakage (at similar sheet resistance) and lower silicide to p+ Si contact resistance than Co silicide. Key material issues impacting the applicability of NiSi to CMOS technologies were investigated. Studies of the kinetics of Ni₂Si growth were used to design a process that avoids excessive silicidation of small features. The thermal degradation mechanisms of NiSi films were also studied. Thin films degraded morphologically with activation energies of 2.4 eV. Thick films degraded morphologically at low temperatures and by transformation to NiSi₂ at high temperatures, suggesting a higher activation energy for the latter mechanism. Pt alloying was shown to help stabilize NiSi films against morphological degradation.     

The improvement of thermal stability of nickel silicide by adding a thin Zr interlayer

This is the first report of a technique for inserting a thin Zr interlayer into a nickel film to improve the thermal stability of the silicide formed from this film. The sheet resistance of resulting Ni(Zr)Si film was lower than 2 Ω/□. X-ray diffraction and Raman spectral analysis showed that only the silicides low resistance phase (NiSi), rather than high resistance phase (NiSi₂), was present in the sandwich structure. This proves that the incorporation of a thin Zr interlayer into NiSi delayed the occurrence of NiSi₂ phase and widened the upper boundary of silicide formation window by about 100 °C. These experimental results could be explained by Gibbs free energy theory. Furthermore, Ni(Zr)Si/Si Schottky diodes were fabricated by rapid thermal annealing at 650, 700, 750 and 800 °C in order to study the I–V characteristics of the SBD diodes. The barrier height generally fixed at 0.63 eV, and the ideality factor was close to 1. These results show that Ni(Zr)Si film is a favorable local interconnection and contact silicide material.     

Effect of a thin W, Pt, Mo, and Zr interlayer on the thermal stability and electrical characteristics of NiSi

It is reported that the thermal stability of NiSi is improved by employing respectively the addition of a thin interlayer metal (W, Pt, Mo, Zr) within the nickel film. The results show that after rapid thermal annealing (RTA) at temperatures ranging from 650 °C to 800 °C, the sheet resistance of formed ternary silicide Ni(M)Si was less than 3 Ω/□, and its value is also lower than that of pure nickel monosilicide. X-ray diffraction (XRD) and raman spectra results both reveal that only the Ni(M)Si phase exists in these samples, but the high resistance NiSi₂ phase does not. Fabricated Ni(M)Si/Si Schottky barrier devices displayed good I-V electrical characteristics, with the barrier height being located generally between 0.65 eV and 0.71 eV, and the reverse breakdown voltage exceeding to 40 V. It shows that four kinds of Ni(M)Si film can be considered as the satisfactory local connection and contact material.     

Silicidation of Ni(Yb) Film on Si(001)

The influence of the addition of Yb to Ni on the silicidation of Ni was investigated. The Ni(Yb) film was deposited on a Si(001) substrate by co-sputtering, and silicidation was performed by rapid thermal annealing (RTA). After silicidation, the sheet resistance of the silicide film was measured by the four-point probe method. X-ray diffraction and micro-Raman spectroscopy were employed to identify the silicide phases, and the redistribution of Yb after RTA was characterized by Rutherford backscattering spectrometry and Auger electron spectroscopy. The influence of the Yb addition on the Schottky barrier height (SBH) of the silicide/Si diode was examined by current–voltage measurements. The experimental results reveal that the addition of Yb can suppress the formation of the high-resistivity Ni₂Si phase, but the formation of low-resistivity NiSi phase is not affected. Furthermore, after silicidation, most of the Yb atoms accumulate in the surface layer and only a small number of Yb atoms pile up at the silicide/Si(001) interface. It is believed that the accumulation of a small amount of Yb at the silicide/Si(001) interface results in the SBH reduction observed in the Ni(Yb)Si/Si diode.     

Structural and electrical characterization of platinum (~15 at%) doped nickel silicides on Si(100) and SiGe/Si(100) substrates

Ni(Pt~15 at%)Si/Si(100) and Ni(Pt~15 at%)SiGe/SiGe/Si(100) films corresponding to rapid thermal annealing (RTA1) temperatures of 220, 230 and 240 °C with constant RTA2 (at 420 °C) have been investigated for sub 20 nm devices. X-ray reflectometry (XRR), X-ray diffraction (XRD), four point probe, and atomic force microscopy (AFM) techniques were employed for the characterization of NiSi and NiSiGe films. XRR results indicated that NiSi and NiSiGe film thicknesses increased with RTA1 temperatures. NiSi films densities increased with layer thickness but NiSiGe films displayed an opposite trend. The diffractograms revealed that NiSi and NiSiGe layers contain identical phases and possessed fiber texture at 220 °C. Whereas, the peaks shift were observed for NiSi (211) and NiSi (021) at higher RTA1 temperatures which appear due to Pt diffusion (hexagonal structures of larger grain size were noted). NiSiGe crystallites self-alignment was observed because of strained SiGe/Si(100) substrate. At 240 °C, NiSiGe layer showed the smallest crystallites. This is believed to be due to Pt distributed along the silicide grain boundaries which obstructs silicide grain growth. NiSi and NiSiGe sheet resistance decreased significantly with increase in RTA1 temperatures and found to correlate with multiple grain orientation. AFM revealed a smooth-stable surface morphology for all films.     

New salicidation technology with Ni(Pt) alloy for MOSFETs

A novel salicide technology to improve the thermal stability of the conventional Ni silicide has been developed by employing Ni(Pt) alloy salicidation. This technique provides an effective avenue to overcome the low thermal budget (<700°C) of the conventional Ni salicidation by forming Ni(Pt)Si. The addition of Pt has enhanced the thermal stability of NiSi. Improved sheet resistance of the salicided narrow poly-Si and active lines was achieved up to 750°C and 700°C for as-deposited Ni(Pt) thickness of 30 nm and 15 nm, respectively. This successfully extends the rapid thermal processing (RTP) window by delaying the nucleation of NiSi₂ and agglomeration. Implementation of Ni(Pt) alloyed silicidation was demonstrated on PMOSFETs with high drive current and low junction leakage