Charge trapping in ultrathin hafnium silicate/metal gate stacks

Charge trapping characteristics of MOCVD HfSi/sub x/O/sub y/ (20% SiO/sub 2/) gate stack of n-MOSFETs during substrate injection have been investigated. Positive constant voltage stress (CVS) and constant current stress (CCS) were applied at the gate of TiN-HfSi/sub x/O/sub y/-SiO/sub 2//p-Si n-MOSFETs having EOT of 2 nm. Significant electron trapping is observed from the positive shift of threshold voltage (/spl Delta/V/sub t/) after stress. Curve fitting of the threshold voltage shift data confirms power law dependence for Hf-silicate gate stacks. Charge pumping measurements for both cases showed significant electron trapping at bulk Hf-silicate while interface trap generation was comparatively insignificant. A turn-around effect is noticed for /spl Delta/V/sub t/ as the stress current and voltage increases under CCS and CVS. Dependence of spatial distribution of charge trapping at shallow traps on stress level in the Hf-silicate film and redistribution of trapped charges during and after removal of stress is possibly responsible for the turn-around effect.     

Stress immunity enhancement of the SiN uniaxial strained n-channel metal–oxide–semiconductor field-effect-transistor by channel fluorine implantation

Channel fluorine implantation (CFI) has been successfully integrated with silicon nitride contact etch stop layer (SiN CESL) to investigate electrical characteristics and stress reliabilities of the n-channel metal–oxide–semiconductor field-effect-transistor (nMOSFET) with HfO₂/SiON gate dielectric. Although fluorine incorporation had been used widely to improve device characteristics, however, nearly identical transconductance, subthreshold swing and drain current of the SiN CESL strained nMOSFET combining the CFI process clearly indicates that stress-induced electron mobility enhancement does not affect by the fluorine incorporation. On the other hand, the SiN CESL strained nMOSFET with fluorine incorporation obviously exhibits superior stress reliabilities due to stronger Si–F/Hf–F bonds formation. The channel hot electron stress and constant voltage stress induced threshold voltage shift can be significantly suppressed larger than 26% and 15%, respectively. The results clearly demonstrate that combining the SiN CESL strained nMOSFET with fluorinated gate dielectric using CFI process becomes a suitable technology to further enhance stress immunity.     

Improvement of charge-to-breakdown distribution by fluorine incorporation into thin gate oxides

This paper reports on the effect of fluorine incorporation on gate-oxide reliability, especially the spatial distribution of charge-to-breakdown (Q/sub BD/). Fluorine atoms were implanted into gate electrodes and introduced into gate-oxide films by annealing. Excess fluorine incorporation increased the oxide thickness and degraded not only the reliability of Si/SiO/sub 2/ interfaces but also dielectric-breakdown immunity. However, it was found, for the first time, that appropriate fluorine incorporation into gate-oxide films could dramatically improve Q/sub BD/-distribution tails in Weibull plots, while maintaining both Si/SiO/sub 2/ interface characteristics and average Q/sub BD/ values. The experimental result for a depth profile of fluorine atoms indicated that fluorine atoms are located dominantly at the two interfaces of the gate-oxide film. In addition, the results of infrared (IR) absorption analysis indicated that the strain of SiO/sub 2/ structures is reduced with increasing fluorine doses. We proposed that both strain release and restructuring of the SiO/sub 2/ network by fluorine incorporation are responsible for improving the Q/sub BD/ of weaker oxide films.     

Improvement of interfacial layer reliability by incorporation of deuterium into HfAlOx formed by D/sub 2/O-ALD

Deuterium was incorporated into the HfAlOx /SiON gate dielectric by the use of heavy water (D/sub 2/O) instead of H/sub 2/O in the atomic layer deposition (ALD) process of HfAlOx. The HfAlOx formed by D/sub 2/O-ALD acts as a deuterium reservoir, and the deuterium atoms are effectively incorporated into the SiON after full CMOS processing. It is clarified that the deuterium incorporation suppresses interfacial trap generation and interfacial SiON breakdown, while charge-trapping in the HfAlOx bulk traps is barely affected. The D/sub 2/O-ALD process is useful for improving the interfacial layer reliability under gate negative stress; therefore it is not only effective for HfAlOx, but also for high-/spl kappa//SiO/sub 2/(SiON) gate stacks with other high-/spl kappa/ materials such as HfO/sub 2/ or HfSiON.     

Impacts of gate electrode materials on threshold voltage (V/sub th/) instability in nMOS HfO/sub 2/ gate stacks under DC and AC stressing

Ultrathin nMOSFET hafnium oxide (HfO/sub 2/) gate stacks with TiN metal gate and poly-Si gate electrodes are compared to study the impact of the gate electrode on long term threshold instability reliability for both dc and ac stress conditions. The poly-Si/high-/spl kappa/ interface exhibits more traps due to interfacial reaction than the TiN/high-/spl kappa/ interface, resulting in significantly worse dc V/sub th/ instability. However, the V/sub th/ instability difference between these two stacks decreases and eventually diminishes as ac stress frequency increases, which suggests the top interface plays a minor role in charge trapping at high operating frequency. In addition, ac stress induced interface states (Nit) can be effectively recovered, resulting in negligible G/sub m/ degradation.     

Highly reliable CVD-WSi metal gate electrode for nMOSFETs

In this paper, we first propose an improved chemical vapor deposition (CVD) WSi/sub x/ metal gate suitable for use in nMOSFETs. We studied the relationship between the Si/W ratio of CVD-WSi/sub x/ film and electrical properties of MOSFETs. As a result, it was found that the Si/W ratio strongly affects carrier mobility and the reliability of gate oxide. In the case of higher Si/W ratio, both electron and hole mobility can be improved. For CVD-WSi/sub 3.9/ electrode, electron mobility and hole mobility at 1.2 V of |V/sub g/-V/sub th/| are 331 and 78 cm/sup 2//V/spl middot/s, respectively. These values are almost the same as those for n/sup +/-poly-Si electrode. The improvement of carrier mobility by controlling the Si/W ratio is due to suppression of fluorine contamination in gate oxide. F contamination at the Si/W ratio of 3.9 is found to be less than that at the Si/W ratio of 2.4 from XPS analysis. Workfunction of CVD-WSi/sub 3.9/ gate estimated from C-V measurements is 4.3 eV. In CVD-WSi/sub 3.9/ gate MOSFETs with gate length of 50 nm, a drive current of 636 /spl mu/A//spl mu/m was achieved for off-state leakage current of 35 nA//spl mu/m at power supply voltage of 1.0 V. By using CVD-WSi/sub 3.9/ gate electrode, highly reliable metal gate nMOSFETs can be realized.     

A novel process-compatible fluorination technique with electrical characteristic improvements of poly-Si TFTs

A process-compatible fluorine passivation technique of poly-Si thin-film transistors (TFTs) was demonstrated by employing a novel CF/sub 4/ plasma treatment. Introducing fluorine atoms into poly-Si films can effectively passivate the trap states near the SiO/sub 2//poly-Si interface. With fluorine incorporation, the electrical characteristics of poly-Si TFTs can be significantly improved including a steeper subthreshold slope, smaller threshold voltage, lower leakage current, higher field-effect mobility, and better on/off current ratio. Furthermore, the CF/sub 4/ plasma treatment also improves the reliability of poly-Si TFTs with respect to hot-carrier stress, which is due to the formation of strong Si-F bonds.     

A study of relaxation current in high-/spl kappa/ dielectric stacks

Dielectric relaxation currents in SiO/sub 2//Al/sub 2/O/sub 3/ and SiO/sub 2//HfO/sub 2/ high-/spl kappa/ dielectric stacks are studied in this paper. We studied the thickness dependence, gate voltage polarity dependence and temperature dependence of the relaxation current in high-/spl kappa/ dielectric stacks. It is found that high-/spl kappa/ dielectric stacks show different characteristics than what is expected based on the dielectric material polarization model. By the drain current variation measurement in n-channel MOSFET, we confirm that electron trapping and detrapping in the high-/spl kappa/ dielectric stacks is the cause of the dielectric relaxation current. From substrate injection experiments, it is also concluded that the relaxation current is mainly due to the traps located near the SiO/sub 2//high-/spl kappa/ interface. As the electron trapping induces a serious threshold voltage shift problem, a low trap density at the SiO/sub 2//high-/spl kappa/ interface is a key requirement for high-/spl kappa/ dielectric stack application and reliability in MOS devices.     

Advantages of LDD-only implanted fluorine with submicron CMOStechnologies

The effect of fluorine implantation on the properties of shallow n ⁺/p junctions has been investigated. The novel approach of this work lies in the introduction of fluorine only in the LDD regions of the device and not in the active region underneath the gate. Gated diodes were used as test vehicles to study the effect of the fluorine incorporation. Gated diodes are ideal for measurements of this nature since they are sensitive to changes in the interfacial properties near the gate to diffusion overlap region. Results from electrical device characterization indicate a reduction in gated diode leakage and mid-gap interface state density as the F-implanted dose is increased without causing any significant change in the flat-band voltages. Results also showed that samples with F incorporation tended to be more robust to electrical stress than those without F. Materials analysis indicated reduced junction depths for samples with F introduced in the LDD regions indicating suppression of phosphorus dopant diffusion     

Charge trapping in ultrathin hafnium oxide

The charge trapping properties of ultrathin HfO/sub 2/ in MOS capacitors during constant voltage stress have been investigated. The effects of stress voltage, substrate type, annealing temperature, and gate electrode are presented in this letter. It is shown that the generation of interface-trap density under constant-voltage stress is much more significant for samples with Pt gate electrodes than that with Al gates. The trapping-induced flatband shift in HfO/sub 2/ with Al gates increases monotonically with injection fluence for p-type Si substrates, while it shows a turnaround phenomenon for n-type Si substrates due to the shift of the charge centroid. The trapping-induced flatband shift is nearly independent of stress voltage for p-type substrates, while it increases dramatically with stress voltage for n-type Si substrates due to two competing mechanisms. The trap density can be reduced by increasing the annealing temperature from 500/spl deg/C to 600/spl deg/C. The typical trapping probability for JVD HfO/sub 2/ is similar to that for ALD HfO/sub 2/.     

Evidence for two distinct positive trapped charge components in NBTI stressed p-MOSFETs employing ultrathin CVD silicon nitride gate dielectric

Besides the generation of interface states and the associated positive trapped charge (N/sub tc1/), experimental results unambiguously show the generation of another positive trapped charge component (N/sub tc2/) during negative-bias temperature instability (NBTI) stressing of p-MOSFETs employing ultrathin silicon nitride gate dielectric. For a given gate stress voltage, N/sub tc2/ is generated at a much faster rate compared to N/sub tc1/. Under the pulsed gate condition studied, N/sub tc1/ could almost be completely annihilated, regardless of the NBTI stress voltage, whereas only partial annihilation of N/sub tc2/ is observed. This more resistant nature of N/sub tc2/ to post-stress relaxation has serious implications on the dynamic NBTI reliability of these p-MOSFETs.     

Modeling of tunneling currents through HfO/sub 2/ and (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks

We present a physical modeling of tunneling currents through ultrathin high-/spl kappa/ gate stacks, which includes an ultrathin interface layer, both electron and hole quantization in the substrate and gate electrode, and energy band offsets between high-/spl kappa/ dielectrics and Si determined from high-resolution XPS. Excellent agreements between simulated and experimentally measured tunneling currents have been obtained for chemical vapor deposited and physical vapor deposited HfO/sub 2/ with and without NH/sub 3/-based interface layers, and ALD Al/sub 2/O/sub 3/ gate stacks with different EOT and bias polarities. This model is applied to more thermally stable (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks in order to project their scalability for future CMOS applications.     

Study of FSG/SiO/sub 2/ double interlayer conditions to prevent Al wiring delamination for sub-0.18-/spl mu/m device integration

A double interlayer of high-density plasma fluorinated silica glass (FSG) and SiO/sub 2/ has been developed to control fluorine instability for sub-0.18-/spl mu/m devices. However, the interlayer conditions need further study for robust integration. The authors investigate the optimum conditions to prevent Al wiring delamination. The correlation between the incidence of delamination and F concentration at Ti-SiO/sub 2/ was demonstrated by the three-dimensional mapping of interfacial F concentrations with various thicknesses of SiO/sub 2/ and F contents in FSG. Detailed analysis of the Ti-SiO/sub 2/ interface reveals that the anomalous growth of the interface layer by absorbing F atoms into the Ti layer causes delamination. The properties of SiO/sub 2/, such as the compressive stress and the density of oxygen deficiency, were adjusted to reduce F diffusion. In addition, the thickness was controlled to above 4500 /spl Aring/ to suppress F accumulation at Ti-SiO/sub 2/ to within the permissible level. These conditions resulted in preventing delamination and obtaining integration reliability without increasing the capacitance between adjacent metal lines.     

Characterization and reliability of dual high-k gate dielectric stack (poly-Si-HfO/sub 2/-SiO/sub 2/) prepared by in situ RTCVD process for system-on-chip applications

We investigate for the first time the possibility of integrating chemical vapor deposition (CVD) HfO/sub 2/ into the multiple gate dielectric system-on-a-chip (SoC) process in the range of 6-7 nm, which supports higher voltage (2.5-5 V operation/tolerance). Results show that CVD HfO/sub 2/-SiO/sub 2/ stacked gate dielectric (EOT =6.2 nm) exhibits lower leakage current than that of SiO/sub 2/ (EOT =5.7 nm) by a factor of /spl sim/10/sup 2/, with comparable interface quality (D/sub it//spl sim/1/spl times/10/sup 10/ cm/sup -2/eV/sup -1/). The presence of negative fixed charge is observed in the HfO/sub 2/-SiO/sub 2/ gate stack. In addition, the addition of HfO/sub 2/ on SiO/sub 2/ does not alter the dominant conduction mechanism of Fowler-Nordheim tunneling in the HfO/sub 2/-SiO/sub 2/ gate stack. Furthermore, the HfO/sub 2/-SiO/sub 2/ gate stack shows longer time to breakdown T/sub BD/ than SiO/sub 2/ under constant voltage stress. These results suggest that it may be feasible to use such a gate stack for higher voltage operation in SoC, provided other key requirements such as V/sub t/ stability (charge trapping under stress) can be met and the negative fixed charge eliminated.     

Breakdown characteristics of nFETs in inversion with metal/HfO2 gate stacks

Time zero and time dependent dielectric breakdown (TZBD and TDDB) characteristics of atomic layer deposited (ALD) TiN/HfO₂ high-κ gate stacks are studied by applying ramped and constant voltage stress (RVS and CVS), respectively, on the n-channel MOS devices under inversion conditions. For the gate stacks with thin high-κ layers (?3.3 nm), breakdown (BD) voltage during RVS is controlled by the critical electric field in the interfacial layer (IL), while in the case of thicker high-κ stacks, BD voltage is defined by the critical field in the high-κ layer. Under low gate bias CVS, one can observe different regimes of the gate leakage time evolution starting with the gate leakage current reduction due to electron trapping in the bulk of the dielectric to soft BD and eventually hard BD. The duration of each regime, however, depends on the IL and high-κ layer thicknesses. The observed strong correlation between the stress-induced leakage current (SILC) and frequency-dependent charge pumping (CP) measurements for the gate stacks with various high-κ thicknesses indicates that the degradation of the IL triggers the breakdown of the entire gate stack. Weibull plots of time-to-breakdown (T_BD) suggest that the quality of the IL strongly affects the TDDB characteristics of the Hf-based high-κ gate stacks.     

Intrinsic mobility evaluation of high-/spl kappa/ gate dielectric transistors using pulsed I/sub d/-V/sub g/

A novel intrinsic mobility extraction methodology for high-/spl kappa/ gate stacks that only requires a capacitance-voltage and pulsed I/sub d/-V/sub g/ measurement is demonstrated on SiO/sub 2/ and high-/spl kappa/ gate dielectric transistors and is benchmarked to other reported mobility extraction techniques. Fast transient charging effects in high-/spl kappa/ gate stacks are shown to cause the mobility extracted using conventional dc-based techniques to be lower than the intrinsic mobility.     

Mobility enhancement in TaN metal-gate MOSFETs using tantalum incorporated HfO/sub 2/ gate dielectric

TaN metal-gate nMOSFETs using HfTaO gate dielectrics have been investigated for the first time. Compared to pure HfO/sub 2/, a reduction of one order of magnitude in interface state density (D/sub it/) was observed in HfTaO film. This may be attributed to a high atomic percentage of Si-O bonds in the interfacial layer between HfTaO and Si. It also suggests a chemical similarity of the HfTaO-Si interface to the high-quality SiO/sub 2/-Si interface. In addition, a charge trapping-induced threshold voltage (V/sub th/) shift in HfTaO film with constant voltage stress was 20 times lower than that of HfO/sub 2/. This indicates that the HfTaO film has fewer charged traps compared to HfO/sub 2/ film. The electron mobility in nMOSFETs with HfO/sub 2/ gate dielectric was significantly enhanced by incorporating Ta.     

The effect of gate metal interdiffusion on reliability performance in GaAs PHEMTs

While Ti metal interdiffusion of Ti-Pt-Au gate metal stacks in GaAs pseudomorphic HEMT (PHEMTs) has been explored, the effect of Ti metal interdiffusion on the reliability performance is still lacking. We use a scanning transmission electron microscopy technique to correlate Ti-metal-InGaAs-channel-separation and Ti-sinking-depth with a threshold voltage V/sub T/. It has been found that Ti-sinking-depth is insensitive to V/sub T/. However, Ti metal interdiffusion reduces the separation of the gate metal and InGaAs channel, thus affecting the I/sub dss/ degradation rate. Accordingly, we observe the dependence of /spl Delta/I/sub dss/ on V/sub T/. Devices with less negative V/sub T/ exhibit inferior reliability performance to those devices with more negative V/sub T/. The results provide insight into a critical device parameter, V/sub T/, for optimizing reliability performance based on I/sub dss/ degradation.     

Effect of UV/VUV enhanced RTP on process variation and device performance of metal gate/high-/spl kappa/ gate stacks for the sub-90-nm CMOS regime

We show that UV/VUV-enhanced rapid thermal processing (RTP) in combination with single-wafer processing using a single tool for the fabrication of metal gate/high-/spl kappa/ dielectric gate stacks not only improves overall device performance, but also leads to a significant reduction in process variation at the front end of the CMOS process flow for the sub-90-nm technology node. The gate stacks were fabricated under various UV/VUV conditions. Gate stacks processed under UV/VUV radiation during all processing steps displayed low leakage currents of the order of 10/sup -11/ A/cm/sup 2/. It is shown that the Al-Al/sub 2/O/sub 3/-Si gate stacks processed under UV/VUV conditions also display the lowest variations both in mean leakage current and mean capacitance, as compared to devices where UV/VUV was not used for all the processing steps. Therefore, it can be see that reliance on successive corrective iterations common to automatic process control or standard design simulation can be reduced significantly. As a result, UV/VUV-enhanced RTP has the potential to reduce the effect of process variations on overall device performance, thereby making the overall process more cost effective and time efficient and therefore improving yield and device reliability.     

DC and RF characteristics of E-mode Ga/sub 0.51/In/sub 0.49/P-In/sub 0.15/Ga/sub 0.85/As pseudomorphic HEMTs

The DC and RF characteristics of Ga/sub 0.49/In/sub 0.51/P-In/sub 0.15/Ga/sub 0.85/As enhancement- mode pseudomorphic HEMTs (pHEMTs) are reported for the first time. The transistor has a gate length of 0.8 /spl mu/m and a gate width of 200 /spl mu/m. It is found that the device can be operated with gate voltage up to 1.6 V, which corresponds to a high drain-source current (I/sub DS/) of 340 mA/mm when the drain-source voltage (V/sub DS/) is 4.0 V. The measured maximum transconductance, current gain cut-off frequency, and maximum oscillation frequency are 255.2 mS/mm, 20.6 GHz, and 40 GHz, respectively. When this device is operated at 1.9 GHz under class-AB bias condition, a 14.7-dBm (148.6 mW/mm) saturated power with a power-added efficiency of 50% is achieved when the drain voltage is 3.5 V. The measured F/sub min/ is 0.74 dB under I/sub DS/=15 mA and V/sub DS/=2 V.