Bilateral Testing of Nano-scale Fault-Tolerant Circuits

As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems. Because fault-tolerant hardwares help to mask the effects caused by increased levels of defects, testing the functionality of the chip together with the embedded fault-tolerance becomes a tremendous challenge. In this paper, a new bilateral testing framework for nano circuits is proposed, where multiple stuck-at faults across different modules in a triple module redundancy (TMR) architecture are considered. In addition, a new test generator is presented for the bilateral testing that takes into account the enormous number of bilateral stuck-at faults possible with new types of guidance in the search, and it can generate a set of vectors that can test the TMR-based nano circuit as a single entity. Experimental results reported for ISCAS’85 and ITC99 circuits demonstrate that the bilateral testing can help to capture many more defects which the single stuck-at fault misses.     

An approach to rollback recovery of collaborating mobile agents

Fault-tolerance is one of the main problems that must be resolved to improve the adoption of the agents' computing paradigm. In this paper, we analyze the execution model of agent platforms and the significance of the faults affecting their constituent components on the reliable execution of agent-based applications, in order to develop a pragmatic framework for agent systems fault-tolerance. The developed framework deploys a communication-pairs independent checkpointing strategy to offer a low-cost, application-transparent model for reliable agent-based computing that covers all possible faults that might invalidate reliable agent execution, migration and communication and maintains the exactly-once execution property.     

雷达检测平台故障注入系统研究与设计

应用故障注入方法对系统进行检测是提高系统可靠性的有效途径。针对某型雷达检测系统的特点,通过对故障注入技术的研究,设计出相应的故障注入系统,给出一套完整的故障注入系统框架和软件总体的功能设计,基于集成度高、体积小的单片机系统,可对雷达检测装备系统的容错能力进行考查和验证。该系统可成功注入故障,具有操作简单、实时注入、性价比高、机动性好等突出优点。     

FAULT DETECTION TEST SET FOR TESTABLE REALIZATIONS OF LOGIC FUNCTIONS WITH ESOP EXPRESSIONS

The circuit testable realization and its fault detection for logic functions with ESOP （EXOR-Sum-Of-Products） expressions are studied. First of all, for the testable realization by using XOR gate cascade, a test set with 2n ＋ m ＋ 1 vectors for the detections of AND bridging faults and a test set with 2n ＋ m vectors for the detections of OR bridging faults are presented. Secondly, for the testable realization by using ）（OR gate tree, a test set with 2n ＋ m vectors for the detections of AND bridging faults and a test set with 3n ＋ m ＋ 1 vectors for the detections of OR bridging faults are presented. Finally, a single fault test set with n ＋ 5 vectors for the XOR gate tree realization is presented. Where n is the number of input variables and m is the number of product terms in a logic function.     

Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits

We propose a new static test set compaction method based on a careful examination of attributes of fault coverage curves. Our method is based on two key ideas: (1) fault-list and test-set partitioning, and (2) vector re-ordering. Typically, the first few vectors of a test set detect a large number of faults. The remaining vectors usually constitute a large fraction of the test set, but these vectors are included to detect relatively few hard faults. We show that significant compaction can still be achieved by partitioning faults into hard and easy faults, and compaction is performed only for the hard faults. This significantly reduces the computational cost for static test set compaction without affecting quality of compaction. The second key idea re-orders vectors in a test set by moving sequences that detect hard faults to the beginning of the test set. Fault simulation of the newly concatenated re-ordered test set results in the omission of several vectors so that the compact test set is smaller than the original test set. Experiments on several ISCAS 89 sequential benchmark circuits and large production circuits show that our compaction procedure yields significant test set reductions in low execution times.     

Test generation and scheduling for layout-based detection of bridgefaults in interconnects

This paper presents a new approach to detecting faults in interconnects; the novelty of the proposed approach is that test generation and scheduling are established using the physical characteristics of the layout of the interconnect under test. This includes critical area extraction and a realistic fault model for a structural methodology. Physical layout information is used to model the adjacencies in an interconnect and possible bridge faults with a weighted graph, which is then analyzed to appropriately compact the tests and schedule their execution for (early) detection of bridge faults. Generation and compaction of the test vectors are accomplished by calculating node and edge weight heuristics from the weighted adjacency graph. Simulation has been performed for unweighted and weighted fault models. Results on random interconnects and the local interconnect of a commercially available field-programmable gate array are provided. The advantage of the proposed approach is that, on average, early detection of faults is possible using significantly fewer tests than with previous approaches. A further advantage is that it represents a realistic alternative to adaptive testing because it avoids costly on-line test generation, while still having a small number of vectors     

An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits

In this paper we describe an FPGA-based approach to speed-up fault injection campaigns for the evaluation of the fault-tolerance of VLSI circuits. Suitable techniques are proposed, allowing emulating the effects of faults and observing faulty behavior. The proposed approach combines the efficiency of hardware-based techniques, and the flexibility of simulation-based techniques. Experimental results are provided showing that significant speed-up figures can be achieved with respect to state-of-the-art simulation-based fault injection techniques.     

Testability analysis and fault modeling of BiCMOS circuits

Defect models have been used for testability analysis of BiCMOS circuits and the results have been compared with an analysis of CMOS circuits. Using a nominal point approach, faults generated are classified as logical or performance degradation faults. It is found that logical fault testing can only cover a small percentage of the total fault set, 54% for BiCMOS, versus 69% for equivalent CMOS gates. Delay faults and current faults are analyzed as applied to BiCMOS and CMOS gates. It is shown that logical fault testing in conjunction with either delay fault testing or current fault testing promises the highest fault coverage for BiCMOS logic gates, around 95%.This research was partially supported by the Department of National Defence of Canada, Academic Research Program, grant # 3705-921.     

Using instruction result locality and re-execution to mitigate silent data corruptions

In this paper, a method to mitigate silent data corruptions (SDCs) is proposed. This paper, first, shows and characterizes instruction result locality based on several simulation results and next, proposes an architecture called instruction value history table (VHT) to detect SDCs. In the case of fault detection, extra instruction redundant execution is utilized to assure fault existence. If outcome of the new redundant execution is different from that of previous one, a fault occurred, otherwise the first execution will be correct. In order to correct any detected faults, third redundant execution of the instruction is performed. Having three values from three redundant instruction executions, makes the correction of the fault feasible. The main advantage of this method is to detect any error which is not detectable by traditional protection codes like parity and SEC-DED. In other words, this method detects SDCs or any multiple faults which are not detectable by protection codes. Various soft error injections have been applied on Alpha processor for several PARSEC benchmarks. Experimental results show that the method can detect up to 70% of injected SDCs.     

Automatic generation and compaction of March tests for memoryarrays

Given a set of memory array faults, the problem of computing a compact March test that detects all specified memory array faults is addressed. In this paper, we propose a novel approach in which every memory array fault is modeled by a set of primitive memory faults. A primitive March test is defined for each primitive memory fault. We show that March tests that detect the specified memory array faults are composed of primitive March tests. A method to compact the March tests for the specified memory array faults is described. A set of examples to illustrate the approach is presented. Experimental results demonstrate the productivity gained using the proposed framework     

Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design

Automatic test pattern generation (ATPG) is the next step after synthesis in the process of chip manufacturing. The ATPG may not be successful in generating tests for all multiple stuck-at faults since the number of fault combinations is large. Hence a need arises for highly testable designs which have 100% fault efficiency under the multiple stuck-at fault(MSAF) model. In this paper we investigate the testability of ROBDD based 2×1 mux implemented combinational circuit design. We show that the ROBDD based 2×1 mux implemented circuit is fully testable under multiple stuck-at fault model. Principles of pseudoexhaustive testing and multiple stuck-at fault testing of two level AND-OR gates are applied to one sub-circuit(2×1 mux). We show that the composite test vector set derived for all 2×1 muxes is capable of detecting multiple stuck-at faults of the circuit as a whole. Algorithms to derive test set for multiple stuck-at faults are demonstrated. The multiple stuck-at fault test set is larger than the single stuck-at fault test set. We show that the multiple stuck-at fault test set can be derived from the Disjoint Sum of Product expression which allows test pattern generation at design time, eliminating the need of an ATPG after the synthesis stage.     

Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits

Automatic test pattern generation (ATPG) remains one of themost complex CAD tasks. Therefore, numerous methods were proposed tospeed up ATPG by using parallelism. In this paper, we focus onparallelizing ATPG for stuck-at faults in sequential circuits bycombining fault and search space parallelism. Fault parallelism isapplied to so-called easy-to-detect faults. The main task of thisapproach is to find a best-suited partitioning of the fault list,based on dependencies between faults. For hard-to-detect faultsleft by fault parallelism, search space partitioning is applied,integrating depth-first and breadth-first search. Since a smalltest set size is mandatory for a cheap test and fault parallelismincreases the number of test patterns, test set compaction is donein a post-processing phase. Results show that our approach is notonly capable of achieving potentially superlinear speedups, but alsoimproves test set quality. The parallel environment we use consistsof a network of 100 workstations connected via ethernet.     

An efficient structural approach to board interconnect diagnosis

In this paper we present an efficient structural approach for diagnosing board interconnects using boundary-scan. Whereas existing diagnosis approaches assume only wired-AND or wired-OR bridging fault model, we consider a more complex bridging short fault model in a CMOS circuit environment. The diagnostic test set is generated on the basis of graph theoretic technique and the adjacency fault model is adopted. By using the structural information of the wiring layout, the test length can be reduced. Both one-step and two-step diagnosis algorithms are given. They guarantee the complete diagnosis of multiple interconnect faults with no aliasing or confounding. The algorithms have been evaluated by simulation on several benchmark layouts and randomly generated layouts. Simulation results show that more than 50% reduction in the number of tests can be achieved for two-step diagnosis when the fault rate is very small, such as in a matured product line. This can significantly save the diagnosis cost for boundary-scan testing.     

A New Test Point Selection Method for Analog Continuous Parameter Fault

Discrete hard fault is always tested in existing node selection methods for analog circuit diagnosis. Actually, analog component parameter changes continuously and output node voltages distribute in a continuous voltage interval. In this paper, an novel test node selection method is proposed for continuous parameter shifting (CPS) fault. Firstly, CPS faults are sampled by parameter scan simulation in a single test frequency. Collected node voltages are seen as a data set in a statistical distribution. Secondly, ambiguous faults are identified according to the independent distributions of all CPS faults. The independence of CPS fault sample is deduced by Kruskal-Wallis non-parametric testing. Then, new fault dictionaries are generated for each test node according to ambiguous interval. The proposed fault dictionary represents the mutual independence of each pair of CPS faults. Finally, as fault dictionaries are considered as connected graphs, the optimal test nodes are selected based on an improved depth first search (DFS) algorithm. The effectiveness of method is verified by testing linear and nonlinear circuits.     

Testability of parity checkers

Checkers are used in digital circuits to detect both intermittent and stuck-at faults. The most common error detectors are parity checkers. Such circuits are themselves subject to failures. The use of parity trees is outlined, and techniques for testing them are surveyed. The effect of the checker's structure on its testability is discussed. Several fault models are considered: single stuck-at, multiple stuck-at, and bridging faults. The effectiveness of single stuck-at fault test sets in detecting multiple stuck-at and bridging faults is described. Upper bounds for the double fault coverage of the minimal single fault test are given for different tree structures. The testabilities of some selected checkers are examined to illustrate the concepts developed. A built-in self-test is proposed     

Fault Models for Quantum Mechanical Switching Networks

In classical test and verification one develops a test set separating a correct circuit from a circuit containing any considered fault. Classical faults are modelled at the logical level by fault models that act on classical states. The stuck fault model, thought of as a lead connected to a power rail or to a ground, is most typically considered. A classical test set complete for the stuck fault model propagates both binary basis states, 0 and 1, through all nodes in a network and is known to detect many physical faults. A classical test set complete for the stuck fault model allows all circuit nodes to be completely tested and verifies the function of many gates. It is natural to ask if one may adapt any of the known classical methods to test quantum circuits. Of course, classical fault models do not capture all the logical failures found in quantum circuits. The first obstacle faced when using methods from classical test is developing a set of realistic quantum-logical fault models (a question which we address, but will likely remain largely open until the advent of the first quantum computer). Developing fault models to abstract the test problem away from the device level motivated our study. Several results are established. First, we describe typical modes of failure present in the physical design of quantum circuits. From this we develop fault models for quantum binary quantum circuits that enable testing at the logical level. The application of these fault models is shown by adapting the classical test set generation technique known as constructing a fault table to generate quantum test sets. A test set developed using this method will detect each of the considered faults.     

Fault detection for multiple-valued logic circuits with fanout-free

The single fault and multiple fault detections for multiple-valued logic circuits are studied in this paper. Firstly, it is shown that the cardinality of optimal single fault test set for fanout-free m-valued circuits with n primary inputs is not more than n + 1, for linear tree circuits is two, and for multiplication modulo circuits is two if n is an odd number or if n is an even number and m > 3, where the optimal test set of a circuit has minimal number of test vectors. Secondly, it is indicated that the cardinality of optimal multiple fault test set for linear tree circuits with n primary inputs is 1 + [n/(m - 1)], for multiplication modulo circuits is n + 1, for fanout-free circuits that consist of 2-input linear tree circuits and 2-input multiplication modulo circuits is not greater than n+ 1, where [x] denotes the smallest integer greater than or equal to x. Finally, the single fault location approaches of linear tree circuits and multiplication modulo circuits are presented, and all faults in th