Compact wound-type slot antenna with wide bandwidth

A new type of a slot antenna in which a slot is formed in wound-type around a dielectric substrate is proposed. In comparison with a conventional meander slot antenna, the proposed antenna has a wider bandwidth and smaller size. The proposed antenna has been designed on a gallium arsenide (GaAs) substrate and fabricated by integrated circuit process for the integration of the antenna with active components. The fabricated antenna has dimensions of 6.2 /spl times/4.1 mm/sup 2/ and a 10-dB bandwidth of 300 MHz at 5.8 GHz.     

Compact CPW-fed quasi-circular monopole with very wide bandwidth

Presented is a new CPW-fed quasi-circular monopole antenna, which is composed of a triangle and its tangent circle. This smooth monopole structure reduces the dimensions and improves impedance bandwidth dramatically. The CPW ground is bevelled to form a 50 to 100 Omega impedance transformer. The measured bandwidth defined by VSWR<2 is from 2.55 to 18.5 GHz, i.e. a ratio of about 7.3:1. The proposed monopole exhibits a nearly omnidirectional radiation pattern with very compact size and simple structure, which is suitable for various military and commercial wideband applications     

Compact bandpass filters with wide controllable fractional bandwidth

In this letter, complementary split ring resonators (CSRR) are proposed to design bandpass filters (BPFs) having wide controllable 3-dB fractional bandwidth (FBW). FBW can be varied between 10% and 100%. In addition, filters have the advantages of compactness, sharp rejection, low insertion loss (IL), and low cost. Two prototype fabricated filters of FBW 10.8% and 81.6% show a maximum passband IL of 1.2dB. Filter occupying area is less than 0.25/spl lambda//sub g//spl times/0.15/spl lambda//sub g/, where /spl lambda//sub g/ is the guided wavelength at the midband frequency.     

A network-assisted flow mobility architecture for optimized mobile medical multimedia transmission

A large part of mobile Health (mHealth) use-cases such as remote patient monitoring/diagnosis, teleconsultation, and guided surgical intervention requires advanced and reliable mobile communication solutions to provide efficient multimedia transmission with strict medical level Quality of Service (QoS) and Quality of Experience (QoE) provision. The increasing deployment of overlapping wireless access networks enables the possibility to offer the required network resources for ubiquitous and pervasive mHealth services. To address the challenges and support the above use-cases in today’s heterogeneous network (HetNet) environments, we propose a network-assisted flow-based mobility management architecture for optimized real-time mobile medical multimedia communication. The proposed system is empirically evaluated in a Pan-European HetNet testbed with multi-access Android-based mobile devices. We observed that the proposed scheme significantly improves the objective QoE of simultaneous real-time high-resolution electrocardiography and high-definition ultrasound transmissions while also enhances traffic load balancing capabilities of wireless architectures.     

MPEG-4多媒体移动通信系统的一种有效复用结构

介绍了一种基于MPEG－4标准的移动多媒体的两层复用结构。第一层对有相似服务质量（QoS）要求的基本数据流进行打包，形成具有较少QoS要求的数据流；第二层为每个数据流提供相应的防误码措施，形成可在易误码链路进行传输的单一数据流，达到既满足各个基本数据流防误码的要求,又使复用开销最小。     

满足多媒体处理器需求的动态电源管理技术

本文将介绍相关多媒体处理器的电源管理技术原理,以及如何利用这些技术降低功耗,并讨论采用哪些外部电源管理器件和功率IC可确保处理器芯片全面发挥省电特性.     

Multimedia IP architecture trends in the mobile multimedia consumer device

A dedicated media processor is used in many mobile consumer devices to accelerate video, image, graphics, and display processing. Increased demand for higher pixel resolution, higher quality image and video processing, more graphics performance necessitates dramatically increased signal processing capabilities. To provide the increased performance at acceptable cost and power requires redesign of the traditional architecture. By wisely partitioning algorithms across programmable and fixed-function blocks, the performance goals can be met while still maintaining flexibility for new feature requirements and new standards. For a better than acceptable user experience and playback time, all IPs (display, graphics, video, and imaging) have to be optimized as an “end to end” system. In this paper, an overview of the future trends of multimedia IP processor architectures is provided that describes the implications on system architecture, power, and performance.     

Variable precision arithmetic circuits for FPGA-based multimedia processors

This brief describes new efficient variable precision arithmetic circuits for field programmable gate array (FPGA)-based processors. The proposed circuits can adapt themselves to different data word lengths, avoiding time and power consuming reconfiguration. This is made possible thanks to the introduction of on purpose designed auxiliary logic, which enables the new circuits to operate in single instruction multiple data (SIMD) fashion and allows high parallelism levels to be guaranteed when operations on lower precisions are executed. The new SIMD structures have been designed to optimally exploit the resources of a widely used family of SRAM-based FPGAs, but their architectures can be easily adapted to any either SRAM-based or antifuse-based FPGA chips.     

High-performance embedded SOI DRAM architecture for the low-powersupply

This paper presents the high-performance DRAM array and logic architecture for a sub-1.2-V embedded silicon-on-insulator (SOI) DRAM. The degradation of the transistor performance caused by boosted wordline voltage level is distinctly apparent in the low voltage range. In our proposed stressless SOI DRAM array, the applied electric field to the gate oxide of the memory-cell transistor can he relaxed. The crucial problem that the gate oxide of the embedded-DRAM process must be thicker than that of the logic process can be solved. As a result, the performance degradation of the logic transistor can be avoided without forming the gate oxides of the memory-cell array and the logic circuits individually. In addition, the data retention characteristics can be improved. Secondly, we propose the body-bias-controlled SOI-circuit architecture which enhances the performance of the logic circuit at sub-1.2-V power supply voltage, Experimental results verify that the proposed circuit architecture has the potential to reduce the gate-delay time up to 30% compared to the conventional one. This proposed architecture could provide high performance in the low-voltage embedded SOI DRAM     

New three-dimensional memory array architecture for futureultrahigh-density DRAM

In this paper, a three-dimensional (3-D) memory array architecture is proposed. This new architecture is realized by stacking several cells in series vertically on each cell located in a two-dimensional array matrix. Therefore, this memory array architecture has a conventional horizontal row and column address and new vertical row address. The total bit-line capacitance of this proposed architecture's DRAM is suppressed to 37% of normal DRAM when one bit-line has 1-Kbit cells and the same design rules are used. Moreover, an array area of 1-Mbit DRAM using the proposed architecture is reduced to 11.5% of normal DRAM using the same design rules. This proposed architecture's DRAM can realize small bit-line capacitance and small array area simultaneously. Therefore, this proposed 3-D memory array architecture is suitable for future ultrahigh-density DRAM     

Word-line architecture for highly reliable 64-Mb DRAM

A unique word-line voltage control method for the 64-Mb DRAM and beyond is proposed. It realizes a constant lifetime for a thin gate oxide. This method controls word-line voltage and compensates reliability degradation in the thin gate oxide for cell-transfer transistors. It keeps the time-dependent dielectric breakdown (TDDB) lifetime constant under any conditions of gate oxide thickness fluctuation, temperature variation, and supply voltage variation. This method was successfully implemented in a 64-Mb DRAM to realize high reliability. This chip achieved a 10⁵ times reliability improvement and a 0.3~1.8-V larger word-line voltage margin to write ONE data into the cell     

A programmable NMOS DRAM controller for microcomputer systems with dual-port memory and error checking and correction

An NMOS DRAM controller for use in microcomputer systems based on the iAPX-86 and iAPX-286 microprocessor families or on the Multibus system bus is described. The controller provides complete support for dual-port memories and memories with error checking and correction. The controller has programmable attributes for configuring it to the particular requirements of the system. The controller uses parallel arbitration to minimize arbitration delay. A memory cycle will start on the same clock edge that samples a command if the cycle has been previously enabled. Novel logic and circuit design techniques have been used to achieve 16 MHz operation, 20 ns input setup time, and 35 ns output delay time.     

Streaming processors for next-generation mobile imaging applications

Next-generation mobile devices will continue to demand high processing power for imaging applications. The expected performance is in the class of supercomputers, but delivered with limited energy and memory bandwidth for embedded systems. This article advocates a streaming computation model that leverages the deterministic access patterns in imaging applications to deliver the necessary processing throughput. A reconfigurable datapath connects a set of functional units, forming a computation pipeline to offer energy efficiency. The architecture and implementation of a stream processor are presented along with the memory subsystem to support stream data transfers. The results show speedup ranging from a factor of 2 to 28 for imaging applications, offering favorable comparison against scalar processors.     

Tiered bandwidth reservation scheme for multimedia wireless networks

It is important to provide quality of service (QoS) guarantees if we want to support multimedia applications over wireless networks. In this paper, considering the features of tiering in sectored cellular networks, we propose a novel scheme for bandwidth reservation to approach QoS provisioning. By predicting the movement of each connection, the reserving of bandwidth is only required in needful neighboring cells instead of in all neighboring cells. In addition, an admission control mechanism incorporated with bandwidth borrowing assists in distributing scarce wireless bandwidth in more adaptive way. Through mathematical analysis, we proof the advantages of tier‐based approach and the bound for the selection of tiered boundary. The simulation results also verify that our scheme can achieve superior performance than traditional schemes regarding no bandwidth reserving, fixed bandwidth reserving, and bandwidth borrowing in sectored cellular networks when performance metrics are measured in terms of the connection dropping probability (CDP), connection blocking probability (CBP), and bandwidth utilization (BU). Copyright © 2008 John Wiley & Sons, Ltd.     

Dynamic-Grouping bandwidth reservation scheme for multimedia wireless networks

In wireless networks carrying multimedia traffic (voice, video, data, and image), it becomes necessary to provide a quality-of-service(QoS) guarantee for multimedia traffic connections supported by the network. In order to provide mobile hosts with high QoS in the next-generation wireless networks, efficient and better bandwidth reservation schemes must be designed. This paper presents a novel dynamic-grouping bandwidth reservation scheme as a solution to support QoS guarantees in the next-generation wireless networks. The proposed scheme is based on the probabilistic resource estimation to provide QoS guarantees for multimedia traffic in wireless cellular networks. We establish several reservation time sections, called groups, according to the mobility information of mobile hosts of each base station. The amount of reserved bandwidth for each base station is dynamically adjusted for each reservation group. We use the dynamic-grouping bandwidth reservation scheme to reduce the connection blocking rate and connection dropping rate, while increasing the bandwidth utilization. The simulation results show that the dynamic-grouping bandwidth reservation scheme provides less connection-blocking rate and less connection-dropping rate and achieves high bandwidth utilization.     

Low power wide gates for modern power efficient processors

In this paper, a low power register file and tag comparator is proposed which has lower leakage and higher noise immunity without dramatic speed degradation due to the wide fan-in gates. Simulation of register files and tag comparators designed is done using low-V_th 90 nm CMOS process technology model in all process corners. The results demonstrate 20% power reduction and 2× noise-immunity improvement in the implemented register file using the proposed circuit at the same delay compared to the standard domino circuits. On the other hand, simulation of tag comparators implemented using the other proposed circuit shows 41%, 22% and 7.5% reduction in power, delay and area, respectively compared to the standard footless domino at the same robustness condition. Moreover, the register file and the tag comparator designed with the proposed circuits respectively show 2.48 and 3 times improvement in the defined figure of merit compared to the counterpart circuits designed with the conventional domino circuit. Thus, the proposed are power efficient and suitable approaches for embedded processors with multi-ported register file and fully-associative caches with large number of tag comparators.     

A time-efficient architecture for multimedia applications

This paper presents an architecture that enforces time requirements and gives minimal end-to-end delays for multimedia applications. The layers and mechanisms allowing the system to fulfill the selected synchronization, i.e., the logical relationships and timed interval semantics, are presented. The proposed approach relies on the use of a formal model based on extended time Petri nets, i.e., the time stream Petri net model (TStreamPN), that allows the user to completely specify the time requirements of a given application. The architecture implements, in the application layer and on top of asynchronous environments, the requested quality of service (perceived by the user) with respect to time. At the transport layer, the use of a partial order transport service improves the reactive response of the communication transfers. Its principles are presented together with a presynchronization sublayer that makes the partial order transport service match the applicative synchronization requirements. Moreover, measurements on the implementation of a videoconference system show that the requirements of the quality of service are fulfilled     

Area-efficient special function unit for mobile vertex processors

An area-efficient special function unit (SFU) for the evaluation of transcendental functions in mobile vertex processors is presented. In spite of infrequent usage, previous implementation of an SFU occupied significant portion of a shader datapath unit. The proposed SFU reduces the area by 54% by performing quadratic interpolation included in the function evaluation with a shared 4D dot product unit and implementing setup circuitry and a lookup table by dedicated hardware for the SFU. By benchmarking shader programs, the performance/area of a shader datapath unit turns out to be improved by 69%.     

A general architecture in support of interactive, multimedia, location-based mobile applications

The widespread use of cellular telephones and the availability of user-location information are facilitating the development of new personalized, location-based applications. However, as of today, most of these applications are unidirectional and text-based where the user subscribes and the system sends a text message when appropriate. This article describes a modular and general architecture that supports the development of interactive, multimedia, location-based applications, providing an extra level of service to the users. The flexibility of the architecture is demonstrated by presenting the wireless safety security system (Wi-Via) and other potential applications     

Low-power 3D graphics processors for mobile terminals

A full 3D graphics pipeline is investigated, and optimizations of graphics architecture are assessed for satisfying the performance requirements and overcoming the limited system resources found in mobile terminals. Two mobile 3D graphics processor architectures, RAMP and DigiAcc, are proposed based on the analysis, and a prototype development platform (REMY) is implemented. REMY includes a software graphics library and simulation environment developed for more flexible realization of mobile 3D graphics. The experimental results demonstrate the feasibility of mobile 3D graphics with 3.6 Mpolygons/s at 155 mW power consumption for full 3D operation.