Ta2O5介质膜和Ta2O5—SiO双层介质膜绝缘特性的实验研究

本文介绍了采用直流磁控反应溅射沉积的Ta_2O_5介质膜及由用同样方法沉积的Ta_2O_5膜和电阻式蒸发沉积的SiO膜组成的双层介质膜的绝缘特性。     

Ta2O5介质膜性能对液体钽电容器性能的影响

叙述了钽电解电容器阳极Ta2O5介质膜的形成过程,分析了电解液闪火与氧化膜击穿的微观过程。利用扫描电子显微镜(SEM)分析了阳极氧化后及产品失效后阳极钽芯表面介质膜的微观结构,并对液钽电容器失效机理进行了探讨。结果表明,介质膜内杂质或缺陷处O2-放电产生的电子发射是电解液闪火和氧化膜击穿的前驱点;在高电场或高温度的作用下,介质膜的场致晶化和热致晶化是液体钽电解电容器失效的主要模式。     

Ta2O5Ni60激光熔覆层的耐蚀性研究

利用激光熔覆技术,在A3钢表面进行了Ni60合金添加Ta2O5的激光熔覆实验.采用静态浸泡法对相同工艺条件下获得的纯Ni60熔覆层和Ta2O5/Ni60熔覆层的耐腐蚀性进行了研究.在光学显微镜下观察样品表面腐蚀形貌,并对Ta2O5/Ni60熔覆层的腐蚀机理进行了分析.结果表明:在Ni60自熔合金粉末中加入Ta2O5,可以形成一种新的耐腐蚀体系.然而加入的Ta2O5必须有足够的量(＞7wt.%),才有提高耐蚀性的作用.随着Ta2O5的加入量的增加,试样的耐腐蚀性也增加.当Ta2O5的加入量为11wt.%时,可以使耐蚀性提高20%.     

Ta2O5对TiO2基压敏陶瓷半导化的影响

研究Ta2O5对（Sr，Bt，St，Ta）掺杂的TiO2基压敏陶瓷半导化的影响，发现随着Ta2O5增加，晶粒电阻呈现“U”字型变化规律，按照配方TiO2＋0．3％（SrCO3＋Bt2O3＋SiO2）＋0．1%Ta2O5（摩尔分数）配制的样品的晶粒电阻最小，这表明适当增加施主Ta2O5的含量有助于材料晶粒的半导化。     

SiO2/Ta界面反应及其对铜扩散的影响

利用磁控溅射方法在表面有SiO2层的Si基片上溅射Ta/NiFe薄膜,采用X射线光电子能谱(XPS)研究了SiO2/Ta界面以及Ta5Si3标准样品,并进行计算机谱图拟合分析.实验结果表明在制备态下在SiO2/Ta界面处发生了热力学上有利的化学反应:37Ta+15SiO2=5Ta5Si3+6Ta2O5,界面处形成更稳定的化合物新相Ta5Si3、Ta2O5.在采用Ta作阻挡层的ULSI铜互连结构中这些反应产物可能有利于对Cu扩散的阻挡.     

Structural and electrical characteristics of lanthanum oxide gate dielectric film on GaAs pHEMT technology

This paper investigates the feasibility of using a lanthanum oxide thin film (La_2O_3) with a high dielectric constant as a gate dielectric on GaAs pHEMTs to reduce gate leakage current and improve the gate to drain breakdown voltage relative to the conventional GaAs pHEMT. An E/D mode pHEMT in a single chip was realized by selecting the appropriate La_2O_3 thickness. The thin La_2O_3 film was characterized: its chemical composition and crystalline structure were determined by X-ray photoelectron spectroscopy and X-ray diffraction, respectively.La_2O_3 exhibited good thermal stability after post-deposition annealing at 200, 400 and 600 ℃ because of its high binding-energy (835.6 eV). Experimental results clearly demonstrated that the La_2O_3 thin film was thermally stable.The DC and RF characteristics of Pt/La_2O_3/Ti/Au gate and conventional Pt/Ti/Au gate pHEMTs were examined.The measurements indicated that the transistor with the Pt/La_2O_3/Ti/Au gate had a higher breakdown voltage and lower gate leakage current. Accordingly, the La_2O_3 thin film is a potential high-k material for use as a gate dielectric to improve electrical performance and the thermal effect in high-power applications.     

Source-field-plated Ga2O3 MOSFET with a breakdown voltage of 550 V

Ga_2O_3 metal–oxide–semiconductor field-effect transistors(MOSFETs) with high-breakdown characteristics were fabricated on a homoepitaxial n-typed β-Ga_2O_3 film, which was grown by metal organic chemical vapor deposition(MOCVD) on an Fedoped semi-insulating(010) Ga_2O_3 substrate. The structure consisted of a 400 nm unintentionally doped(UID) Ga_2O_3 buffer layer and an 80 nm Si-doped channel layer. A high k HfO_2 gate dielectric film formed by atomic layer deposition was employed to reduce the gate leakage. Moreover, a source-connected field plate was introduced to enhance the breakdown characteristics. The drain saturation current density of the fabricated device reached 101 mA/mm at V_gs of 3 V. The off-state current was as low as 7.1 ×10^-11 A/mm, and the drain current I_ON/I_OFF ratio reached 10~9. The transistors exhibited three-terminal off-state breakdown voltages of 450 and 550 V, corresponding to gate-to-drain spacing of 4 and 8 μm, respectively.     

不同方法制备的Ta2O5薄膜光学性能和激光损伤阈值的对比分析

采用电子束蒸发(EBE)和离子柬溅射(IBS)制备了不同的Ta2O5薄膜,同时对电子束蒸发制备的薄膜进行了退火处理.研究了制备的Ta2O5薄膜的光学性能、激光损伤阈值(LIDT)、吸收、散射、粗糙度、微缺陷密度和杂质含量.结果表明,退火可使电子束蒸发制备的薄膜的光学性能得到改善,接近离子柬溅射的薄膜的光学性能.电子束蒸发制备的薄膜的损伤阈值较低的主要原因在于吸收大,微缺陷密度和杂质含量高,而与薄膜的散射和粗糙度关系不大.退火后薄膜的吸收和微缺陷密度都明显降低,损伤阈值得到提高.退火后的薄膜损伤阈值仍然低于溅射得到的薄膜损伤阈值是因为退火并不能降低膜内的杂质含量,因此选用高纯度的蒸发膜料和减少电子柬蒸发过程中的污染有可能进一步提高薄膜的损伤阈值.     

MnCO3对BMT系陶瓷结构和微波特性的影响

研究了w(MnCO3)从0．5％～5％(质量分数)对复合钙钛矿Ba(Mg1／3Ta2/3)O3(BMT)系陶瓷结构和微波特性的影响。对于w(MnCO3)为0．5％的BMT系陶瓷,其主晶相为1：2有序六方超晶格和无序立方结构,相应于最大的品质因数与频率的积(Qf)值。随着w(MnCO3)的增加,其Qf值下降。介电常数ε随w(MnCO3)的增大而略有下降,这是由于附加相Ba0.5TaO3影响所致。     

Dual-metal gate CMOS technology with ultrathin silicon nitride gatedielectric

We report the first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor field effect transistors (P-MOSFETs), respectively. The gate dielectric stack consists of a silicon oxy-nitride interfacial layer and a silicon nitride (Si₃N₄) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities comparable to that predicted by the universal mobility model for silicon dioxide (SiO₂) are observed     

Ta2O5/silicon barrier height measured fromMOSFETs fabricated with Ta2O5 gate dielectric

N-channel metal oxide semiconductor field effect transistors with Ta₂O₅ gate dielectric were fabricated. The Ta₂O₅/silicon barrier height was calculated using both the lucky electron model and the thermionic emission model. Based on the lucky electron model, a barrier height of 0.77 eV was extracted from the slope of the ln(I_g/I_d) versus ln(I_sub/I_d) plot using an impact ionization energy of 1.3 eV. Due to the low barrier height, the application of Ta₂ O₅ gate dielectric transistors is limited to low supply voltage preferably less than 2.0 V     

表面预处理对HfO2栅介质MOS器件漏电特性的影响

采用反应磁控溅射方法,在Si衬底上制备了不同表面预处理和不同后退火处理的HfO2栅介质MOS电容。测量了器件的C-V和I-V特性,并进行了高场应力实验。器件的界面特性和栅极漏电机理分析表明,界面态和氧化物陷阱是引起大的栅极漏电流的主要因素。采用新颖的O2 CHCl3(TCE)表面预处理工艺,可以显著降低界面态和氧化物陷阱密度,从而大大减小栅极漏电流和SILC效应。     

Monitoring the Channel Formation in Organic Field‐Effect Transistors via Photoinduced Charge Transfer

Conducting channel formation in organic field‐effect transistors (OFETs) is considered to happen in the organic semiconductor layer very close to the interface with the gate dielectric. In the gradual channel approximation, the local density of accumulated charge carriers varies as a result of applied gate bias, with the majority of the charge carriers being localized in the first few semiconductor monolayers close to the dielectric interface. In this report, a new concept is employed which enables the accumulation of charge carriers in the channel by photoinduced charge transfer. An OFET employing C₆₀ as a semiconductor and divinyltetramethyldisiloxane‐bis(benzocyclobutene) as the gate dielectric is modified by a very thin noncontinuous layer of zinc‐phthalocyanine (ZnPc) at the semiconductor/dielectric interface. With this device geometry, it is possible to excite the phthalocyanine selectively and photogenerate charges directly at the semiconductor/dielectric interface via photoinduced electron transfer from ZnPc onto C₆₀. Thus the formation of a gate induced and a photoinduced channel in the same device can be correlated.     

具有低电压、低“迟滞效应”的C60薄膜晶体管

以C60为激活层,同时以聚合物/高K氧化物双绝缘层结构研制了N型有机场效应晶体管。结果表明,采用这种双层结构的绝缘层能够很好的将Ta2O5和PMMA的优点结合在一起,即既利用了Ta2O5的高介电常数又利用了PMMA与半导体层良好的界面接触特性。与采用单一Ta2O5或这PMMA绝缘层的器件相比,这种具有双层结构的器件性能大幅提升。最终研制了能够在10V低电压下正常工作的C60晶体管,其场效应迁移率、阈值电压和开关电流比分别为0.26 cm2/Vs, 3.2V和8.31×104。同时,利用修饰绝缘层PMMA的疏水性大大降低了这种具有双层结构的N型有机晶体管的“迟滞效应”,从而让器件工作时有较好的稳定性。     

非晶ErAlO高k栅介质薄膜的制备及性能研究

采用射频磁控溅射法在p型Si(100)衬底上成功制备了非晶Er2O3-Al2O3(ErAlO)栅介质复合氧化物薄膜。研究了ErAlO薄膜的结构及电学特性。XRD测量显示,ErAlO薄膜具有良好的热稳定性,样品经过900℃氧气氛退火30 min后仍保持非晶态结构。AFM照片显示,其表面粗糙度小于0.2 nm,平整度良好。ErAlO栅MOS结构在氧分压为1%时,薄膜的有效相对介电常数为9.5,外加偏压(Vg)为–1 V时样品的漏电流密度为7.5×10–3 A/cm2。非晶ErAlO薄膜是一种很有希望取代SiO2的新型高k栅介质候选材料。     

TaC/Ni60激光熔覆层的耐蚀性研究

采用静态浸泡法对原位生成TaC颗粒强化镍基激光熔覆层的耐腐蚀性进行研究.使用金相显微镜和X射线衍射仪对熔覆层进行显微组织和物相分析,在光学显微镜下观察样品表面腐蚀形貌.结果表明:含10wt%(Ta2O5, C)的TaC/Ni60镍基复合涂层在10%H2SO4溶液和10%HCl溶液中均表现出较好的耐腐蚀性能,与纯Ni60激光熔覆层相比,其相对耐蚀性提高50%.     

The observation of negative transconductance effect caused byreal-space-transfer of electrons in metal oxide semiconductor fieldeffect transistors fabricated with Ta2O5 gatedielectric

N-channel metal oxide semiconductor field effect transistors (MOSFETs) with Ta₂O₅ gate dielectric were fabricated. An intrinsic Ta₂O₅/silicon barrier height of 0.51 eV was extracted from the gate current. The effective Ta ₂O₅/silicon barrier height including image force barrier lowering is about 0.37 eV with drain to source voltage V_DS ranging from 1.5 V to 4.0 V. Due to the low barrier height, negative transconductance effect was observed in the linear region. The decrease of drain current is due to the real space transfer of electrons from the drain terminal to the gate electrode     

TaN wet etch for application in dual-metal-gate integration technology

Wet-etch etchants and the TaN film method for dual-metal-gate integration are investigated. Both HF/HN O_3/H_2O and NH_4OH/H_2O_2 solutions can etch TaN effectively, but poor selectivity to the gate dielectric for the HF/HNO_3/H_2O solution due to HF being included in HF/HNO_3/H_2O, and the fact that TaN is difficult to etch in the NH_4OH/H_2O_2 solution at the first stage due to the thin TaO_xN_y layer on the TaN surface, mean that they are difficult to individually apply to dual-metal-gate integration. A two-step wet etching strategy using the HF/HNO_3/H_2O solution first and the NH_4OH/H_2O_2 solution later can fully remove thin TaN film with a photo-resist mask and has high selectivity to the HfSiON dielectric film underneath. High-k dielectric film surfaces are smooth after wet etching of the TaN metal gate and MOSCAPs show well-behaved C-V and J_g-V_g characteristics, which all prove that the wet etching of TaN has little impact on electrical performance and can be applied to dual-metal-gate integration technology for removing the first TaN metal gate in the PMOS region.     

大口径1064nm窄带滤光片的研制

采用现代光通信DWDM镀膜技术,选用Ta2O5/SiO2氧化物硬质薄膜材料,研制成功大口径、高性能1064nm窄带滤光片。给出了从膜系设计到试生产及膜层的性能方面的一些实验结果,表明产品的各项性能指标达到或超过了客户的要求,现已定型批量生产。     

Fully solution-processed organic thin-film transistors by consecutive roll-to-roll gravure printing

A high-performance/flexible organic thin-film transistor (OTFT) is fabricated by using all-step solution processes, which are composed of roll-to-roll gravure, plate-to-roll gravure and inkjet printing with the least process number of 5. Roll-to-roll gravure printing is used to pattern source/drain electrodes on plastic substrate while semiconductor and dielectric layers are printed by consecutive plate-to-roll gravure printing. Finally, inkjet printing of Ag organometallic ink is used to pattern the gate electrode. The fabricated OTFT exhibits excellent electrical performance, field-effect mobility over 0.2 cm²/Vs, which is one of the best compared to the previous works. The deposition of a self-assembled monolayer on the source-drain electrodes results in a higher work function which is suitable for a p-type polymer semiconductor. Moreover, the formation of dense gate electrode line on hydrophobic dielectric is achieved by selecting suitable Ag ink.