AND/XOR电路低功耗映射及其在最佳混合极性搜索中的应用

本文提出一种工艺无关的AND/XOR电路低功耗映射算法。该算法通过优化电路节点开关活动性实现静态MPRM电路平均功耗最小化,根据给定工艺库中的逻辑门估算MPRM电路的功耗和面积。在此基础上,结合极性转换算法获得任意极性的MPRM电路,利用遍历搜索法快速找到最佳混合极性。通过对18个MCNC和ISCAS基准电路测试表明：与FPRM电路和AND/OR电路功耗优化方案相比,混合极性搜索方案获得的AND/XOR电路功耗平均节省分别可达44.22%和60.09%,面积平均节省分别可达14.13%和32.72%。     

基于动态逻辑的MPRM电路低功耗优化设计

n个输入变量的逻辑函数有3n种不同的MPRM(Mixed-Polarity Reed-Muller)表达式,其对应电路的功耗和面积不尽相同。本文通过对CMOS电路功耗和动态逻辑MPRM电路低功耗分解方法的分析,建立MPRM电路功耗和面积估计模型,而后提出一种基于动态逻辑的MPRM电路快速低功耗分解算法。在此基础上,针对中小规模和大规模MPRM电路,结合列表转换技术,分别将穷尽搜索算法和遗传算法应用于基于动态逻辑的MPRM电路低功耗优化设计中。通过对MCNC和ISCAS基准电路测试表明:与Boolean电路和FPRM(Fixed-Polarity Reed-Muller)电路相比,中小规模MPRM电路的功耗平均节省80.65%和50.98%,大规模MRPM电路的功耗平均节省69.17%和46.61%。     

CMOS异或电路的设计与应用

设计了四种CMOS"异或"单元电路,通过模拟仿真分析了它们各自的性能特点,并讨论了它们在奇偶检测电路、微处理器系统加法器电路以及单片机全加电路等设计中的不同应用.     

PMGA and its application in area and power optimization for ternary FPRM circuit

Based on the research of population migration algorithms (PMAs), a population migration genetic algorithm (PMGA) is proposed, combining a PMA with a genetic algorithm. A scheme of area and power optimization for a ternary FPRM circuit is proposed by using the PMGA. Firstly, according to the ternary FPRM logic function expression, area and power estimation models are established. Secondly, the PMGA is used to search for the best area and power polarity. Finally, 10 MCNC Benchmark circuits are used to verify the effectiveness of the proposed method. The results show that the ternary FPRM circuits optimized by the PMGA saved 13.33% area and 20.00% power on average than the corresponding FPRM circuits optimized by a whole annealing genetic algorithm.     

绝热电路三要素理论及其应用

本文在研究多值电路三要素理论基础上提出绝热电路通用理论，即绝热电路三要素（信号、网络、负载）理论。应用此理论，设计了三种典型的绝热电路（逐级级联收缩结构、可逆逻辑结构和交叉存贮结构），验证了该理论的正确性；然后进一步依此理论设计了一种新颖的采用二相功率时钟的交叉存贮型绝热电路一钟控传输门绝热逻辑（Clocked Transmission Gate Adiabatic Logic，CTGAL）电路。最后用计算机验证了根据绝热电路三要素理论设计的CTGAL电路具有正确的逻辑功能和明显的低功耗特性。     

Design of a DTCTGAL circuit and its application

By research on the switch-signal theory for multiple-valued logic circuits, the theory of three essential elements and the principle of adiabatic circuits, a design scheme for a double power clock ternary clocked transmission gate adiabatic logic (DTCTGAL) circuit is presented. The energy injection and recovery can be conducted by the bootstrapped NMOSFET, which makes the circuit maintain the characteristics of energy recovery as well as multiple-valued input and output. An XOR/XNOR circuit based on DTCTGAL is also presented using this design scheme. Finally, using the parameters of a TSMC 0.25 μm CMOS device, PSPICE simulation results indicate that the proposed circuits have correct logic and significant low power characteristics.     

基于双功率时钟的DTCTGAL电路设计及其应用

By research on the switch-signal theory for multiple-valued logic circuits, the theory of three essential elements and the principle of adiabatic circuits, a design scheme for a double power clock ternary clocked transmission gate adiabatic logic （DTCTGAL） circuit is presented. The energy injection and recovery can be conducted by the bootstrapped NMOSFET, which makes the circuit maintain the characteristics of energy recovery as well as multiple-valued input and output. An XOR/XNOR circuit based on DTCTGAL is also presented using this design scheme. Finally, using the parameters of a TSMC 0.25μm CMOS device, PSPICE simulation results indicate that the proposed circuits have correct logic and significant low power characteristics.     

基于XNOR/OR逻辑的低功耗最佳极性搜索

 本文通过对XNOR/OR逻辑表达式、信号概率传递算法和极性转换算法的研究,提出了一种基于XNOR/OR逻辑的低功耗最佳极性搜索算法.由于算法所用的成本函数包含功耗和面积两方面因素,因此能实现功耗和面积的同时优化.通过对10个MCNC Benchmark电路的测试表明,算法对最佳极性的搜索相当有效:与极性0时的XNOR/OR电路相比,算法搜索到的最佳极性所对应的电路,功耗和面积平均节省分别达到68.4％和34.2％.     

钟控神经MOS管的改进及其在多值电路中的应用

首先对钟控神经MOS管进行研究,提出了相应的改进方法.然后采用此改进的钟控神经MOS管设计了一种新型多值触发器.与传统的触发器相比较,此多值触发器具有结构简单、速度快、功耗低等特点;而且无需改变电路结构就可实现不同基的多值触发器.PSPICE模拟证明了所设计的电路具有正确的逻辑功能.     

航天器低功耗电源控制器测控单元设计

本文针对航天器电源控制器智能化、低功耗等方面的设计需求,对电源控制器遥测遥控接口单元采用智能化控制设计,依托微处理器内部软件来执行电源系统全任务周期的控制和管理,提高电源系统的效率、可靠性、自主管理能力,并降低系统的静态功耗.     

基于SPI总线的电能计量芯片ATT7022及其在配电监测终端的应用

介绍了高精度电能计量芯片ATT7022的主要功能、性能比较、内部结构、接口方式及校表方法等，同时对ATT7022在电能配电监控终端的应用作了简要阐述。     

CPW无空气桥功分器设计及其在阵列天线中的应用

针对传统微带圆极化阵列天线存在带宽较窄、尺寸较大等问题,提出一种新颖的基于共面波导(CPW)槽线转换结构的无空气桥功分器,并基于此功分器设计了一款紧凑型高定向性圆极化阵列天线。设计的共面波导功分器利用共面波导奇模式方法实现了能量分配,不需使用空气桥结构及四分之一波长匹配线,因此尺寸更加紧凑,结构更加简单。利用此功分器设计的圆极化阵列天线剖面厚度仅为1 mm,轴比带宽为4.14%,阻抗带宽为7.03%;在5.8 GHz时,实测增益为8.412 dBi,在保证低剖面、小尺寸的同时,可提供足够的工作带宽以及天线增益。     

集成的B iCMO S DCöD C 开关电源控制器 输出驱动电器的低功耗设计

为使DC／DC开关电源的功率开关管及时地导通或截止,需要设计专用的输出驱动电路,基于整个开关电源系统低功耗的考虑,开关电源可以采用同步整流的拓扑结构。该拓扑结构需要一个电压自举的输出驱动电路,本文首先提出了一种有自举功能的BiCMOS工艺的输出驱动电路,在此基础上,采用电流源和电流沉串联的方式改进了前面提出的输出驱动电路,通过消除CMOS电路的瞬态短路导通现象,不仅降低了该电路模块的功耗,而且起到了保护的作用,经HSPICE模拟表现,开关电源的输入电压Vin为10V控制器内部电压（VL）为5V,开关频率为200kHz时,改进驱动电路的功耗降低了约11．5％,同时避免了瞬态短路导通现象。     

用于12 bit 40 MS/s低功耗流水线ADC的采样保持电路

设计了一个可降低12 bit 40 MHz采样率流水线ADC功耗的采样保持电路。通过对运放的分时复用,使得一个电路模块既实现了采样保持功能,又实现了MDAC功能,达到了降低整个ADC功耗的目的。通过对传统栅压自举开关改进,减少了电路的非线性失真。通过优化辅助运放的带宽,使得高增益运放能够快速稳定。本设计在TSMC0.35μm mix signal 3.3 V工艺下实现,在40 MHz采样频率,输入信号为奈奎斯特频率时,其动态范围(SFDR)为85 dB,信噪比(SNDR)为72 dB,有效位数(ENOB)为11.6 bit,整个电路消耗的动态功耗为14 mW。     

A few CMOS transconductors optimized for low power and wide band operation

Maximizing the bandwidth of operation relative to dc power dissipation in complementary metal oxide semiconductor (CMOS) transconductors has been addressed in this article. It is proposed that the ac transconductance-to-dc power dissipation ratio is an appropriate objective function in this case. The general nature of the objective function is examined first. CMOS transconductors with two and four MOS working transistors are analyzed next. For structures of each kind, the ac transconductance-to-dc power dissipation ratio is maximized, and the optimal set of voltage variables is evaluated. For four-MOS structures with differential input signals, it is revealed that the choice of signal phase influences the objective function. The results of theoretical analyses are exhaustively tabulated. Numerical simulations are used to bring out the significance of the analytical expressions. This facilitates a comparison among several transconductors regarding the best possible ac transconductance-to-dc power dissipation ratio. These results are combined with HSPICE simulation results to suggest a few transconductor structures that are optimum with reference to the operation over wide bandwidths with lower power dissipation, high linearity and low harmonic distortion.The research was supported by grant no. N485 awarded to Dr. R. Raut by the Natural Science and Engineering Research Council (NSERC) of Canada.     

一种降低DMT系统发送信号峰值的非线性映射方法

针对DMT ADSL（DMT线路码非对称数字用户环路）传输系统发送信号幅值尖峰问题。本文提出了一种降低发送信号最大峰值同时又不损失系统 传送信息的非线性映射方法。通过最优化方法合理地设计一组可逆映射器,该方法比目前ADSL系统的硬限幅方法能较大幅度地压缩系统的动态范围或在相同的动态范围下获得更好的传输性能。     

Modeling and design of 3-D MPPT for ultra low power RF energy harvesters

Radio-Frequency (RF) energy harvesting must cope with the limited availability and high variability of the energy source. In this paper, the modeling of an RF harvester for ultra low power environments is presented. A mathematical model based on theoretical analysis is developed. The model demonstrates that the maximum transferred power point is located in a three-dimensional space defined by the input capacitance, the output voltage, and the load resistance of the rectifier circuit. Moreover, the mathematical model returns results in substantial agreement with the SPICE simulation results, while guaranteeing a remarkable reduction of the required computation time. Furthermore, the paper reports the implementation of a mixed signal system for the 3-D MPPT, to be embedded in an RF harvester, in a 65 nm CMOS technology. The circuit exhibits a simulated power consumption lower than 100 nW, making this solution suitable for ultra low power harvesting.     

STC12C5412单片机及其在简易无功控制器中的应用

介绍了STC12C5412单片机及其特点,在此基础上,针对分散无功补偿的低成本要求,利用STC12C5412单片机设计一款简易无功控制器,论述了控制器的硬件结构、工作原理及软件设计.现场运行证实该控制器具有高可靠性低成本的优点,能够满足分散无功补偿的控制要求.     

Relay node selection scheme and deep sleep period for power management in energy-harvesting wireless sensor networks

This paper presents Relay node selection scheme and Deep sleep period for power management in Energy Harvesting Wireless Sensor Networks (RD-EHWSN), a new energy-saving scheme founded on asynchronous duty cycling. RD-EHWSN reduces sensor node energy consumption and guarantees equilibrium energy use between sensor nodes in WSN with the energy harvesting capacity by adjusting these sensor nodes duty cycles more drastically and deeply by according to the estimated value of its residual energy on the basis of future-presented harvested energy, and this is done through the use of a new proposed energy threshold policy. RD-EHWSN also grips the benefit of transmitter initiated using the low power listening (LPL) technique with short preamble messages and uses a new relay node selection procedure to achieve the load balancing in WSN. We implemented RD-EHWSN by using OMNeT++/MiXiM. For evaluation, we compared it with PS-EHWSN, under multiple concurrent multihop traffic flows scenarios and scenarios in which nodes can harvest different energy harvesting rate. In all experiments, RD-EHWSN significantly outperformed the PS-EHWSN scheme; the results of simulation demonstrate that our scheme enhances the general yielding of WSN thru lessening the energy consumption and the mean latency, as well as raising the packet delivery ratio and the throughput. Moreover, RD-EHWSN improves the WSN lifetime and ensures it operates in good condition in the case where the energy harvesting rate is lower by comparing it with the PS-EHWSN scheme.     

基于FPGA实现的高速数据采集系统及其在有源电力滤波器中的应用

有源电力滤波器(APF)是抑制谐波的主要手段之一,其谐波检测环节要求高速采集多路数据.现场可编程门阵列FPGA(Field Programmable Gate Array)器件具有资源丰富、接口灵活等特点,基于FPGA和快速A/D转换器,AD7864提出一种高速数据采集电路,并给出其程序控制算法,通过实验验证其采样效果良好,能够满足APF对信号采样的实际要求.