一种适用于0.8VCMOS助听器的电流模前馈增益控制系统

摘要：本文介绍了一种适用于助听器前端系统的电流模前馈增益控制系统。和传统自动增益控制系统相比,电流模前馈增益控制通过数字增益控制码来实现前端系统总谐波失真的显著降低。为了从麦克风微弱的输出信号中得到数字控制码, 本文提出了用电流模实现的整流电路和电流模状态控制电路.该设计基于0.13微米CMOS工艺. 测试表明芯片可工作于0.6V的电源电压.在电源电压为0.8V下, 输出摆幅500mVp-p的信号总谐波失真在0.06% (-64dB)以下, 且功耗控制在40uW以内.另外,系统的等效输入噪声达到4uVrms,最大增益保持在33dB.     

一种用于数字助听器SoC的高性能低功耗、可配置自动增益控制环路

A low-power,configurable auto-gain control loop for a digital hearing aid system on a chip(SoC) is presented.By adopting a mixed-signal feedback control structure and peak detection and judgment,it can work in automatic gain or variable gain control modes through a digital signal processing unit.A noise-reduction and dynamic range(DR) improvement technique is also used to ensure the DR of the circuit in a low-voltage supply.The circuit is implemented in an SMIC 0.13 μm 1P8M CMOS process.The measurement results show that in a 1 V power supply,1.6 kHz input frequency and 200 mVp-p,the SFDR is 74.3 dB,the THD is 66.1 dB,and the total power is 89 μW,meeting the application requirements of hearing aid SoCs.     

一种用于1V助听器的低功耗增益控制系统

文中提出了一种用于助听器的低功耗增益控制系统.与传统增益控制系统相比,利用两个MRC电路模块同时实现了自动增益控制和指数增益控制功能,有效地降低了系统功耗.同时为了解决传统设计方法在声音压缩工作状态下功耗增加的问题,提出了一种高效增益控制电路,实现了系统从非压缩状态转到压缩状态时,系统功耗的显著降低.该系统在特许半导体公司0.13μm标准CMOS工艺下流片实现,芯片在1V电源电压下的测试结果表明,芯片的功耗控制在45μW以内,且在600mVp-p输出摆幅下的总谐波失真仅为0.3%.     

一种基于前端和后端模块精度优化的助听器系统芯片*

A hearing aid on-chip system based on accuracy optimized front- and back-end blocks is presented for enhancing the signal processing accuracy of the hearing aid. Compared with the conventional system, the accuracy optimized system is characterized by the dual feedback network and the gain compensation technique used in the front-andback-endblocks,respectively,soastoalleviatethenonlinearitydistortioncausedbytheoutputswing.By usingthetechnique,theaccuracyofthewholehearingaidsystemcanbesignificantlyimproved.Theprototypechip has been designed with a 0.13 m standard CMOS process and tested with 1 V supply voltage. The measurement results show that, for driving a 16 loudspeaker with a normalized output level of 300 mV p-p, the total harmonic distortion reached about60 dB, achieving at least three times reduction compared to the previously reported works. In addition, the typical input referred noise is only about 5 υV rms.     

一种平均电流模式控制的单电感双输出型开关电源转换器

An integrated single-inductor dual-output （SIDO） switching DC-DC converter is presented. The outputs are specified with 1.2 V/400 mA and 1.8 V/200 mA. A decoupling small signal model is proposed to analyze the multi-loop system and to design the on-chip compensators. An average current control mode is introduced with lossless, continuous current detection. The converter has been fabricated in a 0.25μm 2P4M CMOS process. The power efficiency is 86% at a total output power of 840 mW while the output ripples are about 40 mV at an oscillator frequency of 600 kHz.     

A single-inductor dual-output switching converter with average current mode control

are about 40 mV at an oscillator frequency of 600 kHz.     

DRM/DAB数字广播无线接收机中高线性电流模第二中频CMOS混频器设计

本文提出了一种用于DRM/ DAB接收机第二中频下变频中的无源开关混频器。该电路由一个输入跨导级,无源电流开关级和电流放大器级构成。输入跨导级采用基于电阻并联反馈自偏置的电流复用技术以提高跨导和输出电阻。开关级引入动态偏置技术以保证开关管过驱动电压随工艺变化的稳定性。电流放大器基于低电压的第二代全平衡多输出电流转换器（FBMOCCII）,引入电流并联负反馈,可提供非常低的输入阻抗及高输出阻抗。设计采用中芯国际0.18微米RF CMOS工艺进行了验证。测试结果表明,该芯片电压增益是1.407dB,噪声指数NF是16.22dB,IIP3为4.5dBm。在1.8V的电源电压下,功耗为9.30mW。该设计体现了增益,噪声和线性度之间的良好折衷,其适合应用在DRM/ DAB无线接收机中的第二中频混频器中。     

应用于射频自动增益控制的CMOS数字校准RMS功率检测器

This paper presents the design and implementation of a digitally calibrated CMOS wideband radio frequency(RF) root-mean-square(RMS) power detector for high accuracy RF automatic gain control(AGC).The proposed RMS power detector demonstrates accurate power detection in the presence of process,supply voltage, and temperature(PVT) variations by employing a digital calibration scheme.It also consumes low power and occupies a small chip area.The measurement results show that the scheme improves the accuracy of the detector to better than 0.3 dB over the PVT variations and wide operating frequency range from 0.2 to 0.8 GHz.Implemented in a 0.18μm CMOS process and occupying a small die area of 263×214μm~2,the proposed digitally calibrated CMOS RMS power detector only consumes 1.6 mA in power detection mode and 2.1 mA in digital calibration mode from a 1.8 V supply voltage.     

一种新型低功耗电流模式CMOS带隙基准设计

为了降低传统带隙基准源的功耗和面积,提出了一种新型基于电流模式高阶曲率修正的带隙基准电压源电路。通过改进的电流模式曲率校正方法实现高阶温度补偿,并且通过集电极电流差生成绝对温度成正比（PTAT）电流,而不是发射极面积差,因此所需电阻以及双极型晶体管（BJT）数量更少。采用标准0.35μm CMOS技术对提出电路进行了具体实现。测量结果显示,温度在-40～130°C之间时,电路温度系数为6.85 ppm/°C,且能产生508.5mV的基准电压。该带隙基准可在电源电压降至1.8 V的情况下工作,在100Hz时,测量所得的电路电源抑制为-65.2dB。在0.1-10 Hz频率范围内,噪声电压均方根输出为3.75 μV。相比其他类似电路,当供电电源为3.3V时,提出电路的整体静态电流消耗仅为9.8μA,面积仅为0.09 mm2。     

一种用于接收机的低功耗自动增益控制环路

This paper proposes a new structure to lower the power consumption of a variable gain amplifier (VGA) and keep the linearity of the VGA unchanged. The structure is used in a high rate amplitude-shift keying (ASK) based IF-stage. It includes an automatic gain control (AGC) loop and ASK demodulator. The AGC mainly consists of six-stage VGAs. The IF-stage is realized in 0.18 μ m CMOS technology. The measurement results show that the power consumption of the whole system is very low. The system consumes 730 μ A while operating at 1.8 V. The minimum ASK signal the system could detect is 0.7 mV (peak to peak amplitude).     

A low power automatic gain control loop for a receiver

This paper proposes a new structure to lower the power consumption of a variable gain amplifier(VGA) and keep the linearity of the VGA unchanged.The structure is used in a high rate amplitude-shift keying(ASK) based IF-stage.It includes an automatic gain control(AGC) loop and ASK demodulator.The AGC mainly consists of sixstage VGAs.The IF-stage is realized in 0.18μm CMOS technology.The measurement results show that the power consumption of the whole system is very low.The system consumes 730μA while oper...     

一种1.8V 0.8～2.1GHz直接变频CMOS正交下变频器

提出了一种CMOS宽带正交直接变频下变频器,片上集成了正交本振相位发生器.混频器采用三段式结构,包括跨导级、开关级和跨阻级作为输出级.跨导级采用互补型结构,在相同的功耗下获得更大的跨导.混频器核心电路未采用电感,能实现在宽频率范围内工作.芯片采用0.18μm CMOS工艺实现,整个变频器在1.8V电源电压下抽取29 m...     

基于平均电流的双闭环APFC电路的设计

为有效消除电力电子设备的谐波干扰,基于UC3855设计了BOOST功率因数校正电路。主电路为减少功率损耗采用ZVT零电压辅助开关。控制电路采用双闭环平均电流模式。利用乘法器校正使输入电流接近正弦波并保持与电压同相位。通过小信号建模推导了电流环、电压环传递函数,配置了系统双环补偿校正网络的参数。最后通过MATLAB仿真和实验验证了设计的正确性。系统的动、稳态性能良好,功率因数接近为1。     

A novel CMOS charge-pump circuit with current mode control 110 mA at 2.7 V for telecommunication systems

This paper presents a novel organization of switch capacitor charge pump circuits based on voltage doubler structures. Each voltage doubler takes a DC input and outputs a doubled DC voltage. By cascading voltage doublers the output voltage increases up to 2 times. A two-phase voltage doubler and a multiphase voltage doubler structures are discussed and design considerations are presented. A simulator working in the Q-V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. To avoid the short circuit during switching, a clock pair generator is used to achieve multi-phase non-overlapping clock pairs. This paper also identifies optimum loading conditions for different configurations of the charge pumps. The proposed charge-pump circuit is designed and simulated by SPICE with TSMC 0.35-μm CMOS technology and operates with a 2.7 to 3.6 V supply voltage. It has an area of 0.4 mm2; it was designed with a frequency regulation of 1 MHz and internal current mode to reduce power consumption.     

一种用于超宽带接收机的CMOS可变增益低噪声放大器

本文介绍一种符合中国超宽带应用标准的工作频率范围为4.2-4.8 GHz的CMOS可变增益低噪声放大器(LNA)。文章主要描述了LNA宽带输入匹配的设计方法和低噪声性能的实现方式,提出一种3位可编程增益控制电路实现可变增益控制。该设计采用0.13-μm RF CMOS工艺流片,带有ESD引脚的芯片总面积为0.9平方毫米。使用1.2 V直流供电,芯片共消耗18 mA电流。测试结果表明,LNA最小噪声系数为2.3 dB,S(1,1)小于-9 dB,S(2,2)小于-10 dB。最大和最小功率增益分别为28.5 dB和16 dB,共设有4档可变增益,每档幅度为4 dB。同时,输入1 dB压缩点是-10 dBm,输入三阶交调为-2 dBm。     

A novel CMOS charge-pump circuit with current mode control 110 mA at 2.7 V for telecommunication systems

This paper presents a novel organization of switch capacitor charge pump circuits based on voltage doubler structures. Each voltage doubler takes a dc input and outputs a doubled dc voltage. By cascading voltage doublers the output voltage increases up to 2 times. A two-phase voltage doubler and a multiphase voltage doubler structures are discussed and design considerations are presented. A simulator working in the Q-V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. To avoid the short circuit during switching, a clock pairs generator is used to achieve multi-phase non-overlapping clock pairs. This paper also identifies optimum loading conditions for different configurations of the charge pumps. The proposed charge-pump circuit is designed and simulated by spice with TSMC 0.35-μm CMOS technology and operates with a 2.7 V to 3.6 V supply voltage. It has an area of 0.4 mm2; it was designed with a frequency regulation of 1 MHz and internal current mode to reduce power consumption.     

A CMOS variable gain LNA for UWB receivers

A CMOS variable gain low noise amplifier(LNA) is presented for 4.2-4.8 GHz ultra-wideband application in accordance with Chinese standard.The design method for the wideband input matching is presented and the low noise performance of the LNA is illustrated.A three-bit digital programmable gain control circuit is exploited to achieve variable gain.The design was implemented in 0.13-μm RF CMOS process,and the die occupies an area of 0.9 mm~2 with ESD pads.Totally the circuit draws 18 mA DC current from 1.2 V DC supply,the LNA exhibits minimum noise figure of 2.3 dB,S(1,1) less than -9 dB and S(2,2) less than -10 dB.The maximum and the minimum power gains are 28.5 dB and 16 dB respectively.The tuning step of the gain is about 4 dB with four steps in all.Also the input 1 dB compression point is -10 dBm and input third order intercept point(IIP3) is -2 dBm.     

一种带有增益提高技术的高速CMOS运算放大器设计

设计了一种用于高速ADC中的高速高增益的全差分CMOS运算放大器。主运放采用带开关电容共模反馈的折叠式共源共栅结构,利用增益提高和三支路电流基准技术实现一个可用于12~14 bit精度,100 MS/s采样频率的高速流水线（Pipelined）ADC的运放。设计基于SMIC 0.25μm CMOS工艺,在Cadence环境下对电路进行Spectre仿真。仿真结果表明,在2.5 V单电源电压下驱动2 pF负载时,运放的直流增益可达到124 dB,单位增益带宽720 MHz,转换速率高达885 V/μs,达到0.1%的稳定精度的建立时间只需4 ns,共模抑制比153 dB。     

Primary side detection and peak current mode control in flyback converter

A new cycle-by-cycle control flyback converter with primary side detection and peak current mode control is proposed and its dynamic characteristics are analyzed.The flyback converter is verified by the OrCAD simulator.The main advantages of this converter over the conventional one are simplicity,small size,rapid regulating and no sensing control signals over the isolation barrier.The circuit is suitable for digital control implementations.