PMOSFET Reliability Study for Direct Silicon Bond (DSB) Hybrid Orientation Technology (HOT)

The use of hybrid orientation technology with direct silicon bond wafers consisting of a (110) crystal orientation layer bonded to a bulk (100) handle wafer provides exciting opportunities for easier migration of bulk CMOS designs to higher performance materials, particularly (110) Si for PMOSFETs for higher hole mobility. In this letter, a 3times mobility improvement and 36% drive current gain were achieved for PMOSFETs on (110) substrates. A systematic investigation of PMOSFET reliability was conducted, and significant degradation of negative bias temperature instability lifetime on (110) orientation was observed due to higher density of dangling bonds. We also report the crystal orientation dependence on ultrathin nitrided gate oxide time-dependent dielectric breakdown.     

Vertical-cavity surface-emitting lasers with spatially adjustableDBR reflectivity to enable free-space photonic repeaters

We have created bidirectional high-performance top- and bottom-emitting vertical-cavity surface-emitting lasers (VCSELs) from a single epitaxial wafer. Using a spatially selective oxidation of AlAs layers in hybrid distributed Bragg reflectors (DBRs) of a VCSEL structure, devices processed for top emission had threshold currents of 100-110 μA with slope efficiencies of 18%-20%. Devices from the same wafer processed for bottom substrate emission had thresholds of 110-120 μA and slope efficiencies of 17% and 18%. This technology will greatly simplify the use of VCSEL's in large three-dimensional (3-D) parallel interconnects, photonic repeaters, and smart pixels     

Comparison of hole mobility in LOCOS-isolated thin-film SOIp-channel MOSFET's fabricated on various SOI substrates

The hole mobility of LOCOS-isolated thin-film silicon-on-insulator (SOI) p-channel MOSFET's fabricated on SOI substrates with different buried oxide thickness has been investigated. Two types of SOI wafers are used as a substrate: (1) SIMOX wafer with 100-nm buried oxide and (2) bonded SOI wafer with 100-nm buried oxide. Thin-film SOI p-MOSFET's fabricated on SIMOX wafer have hole mobility that is about 10% higher than that on bonded SOI wafer. This is caused by the difference in the stress under which the silicon film is after gate oxidation process. This increased hole mobility leads to the improved propagation delay time by about 10%     

面向对注氢硅片中微结构的影响

把不同面向的注氢硅片制成横截面样品,在高分辨率透射电子显微镜下进行观察,发现衬底面向对其中的微结构有明显的影响.首先表现为衬底中主要出现平行于正表面的氢致片状缺陷,即(10 0 )衬底中,主要出现平行于正表面的{ 10 0 }片状缺陷,而(111)衬底中出现的主要是平行于正表面的{ 111}片状缺陷.其原因是注入引起垂直正表面的张应变.另外,面向的影响还表现为,(10 0 )衬底中出现的{ 113}缺陷在(111)衬底中不出现.在(111)衬底中出现的晶格紊乱团和空洞在(10 0 )衬底中不出现.从而推测,{ 111}片状缺陷的形成不发射自间隙原子,而(10 0 )片状缺陷的形成将发射自     

Uniaxial-process-induced strained-Si: extending the CMOS roadmap

This paper reviews the history of strained-silicon and the adoption of uniaxial-process-induced strain in nearly all high-performance 90-, 65-, and 45-nm logic technologies to date. A more complete data set of n- and p-channel MOSFET piezoresistance and strain-altered gate tunneling is presented along with new insight into the physical mechanisms responsible for hole mobility enhancement. Strained-Si hole mobility data are analyzed using six band k/spl middot/p calculations for stresses of technological importance: uniaxial longitudinal compressive and biaxial stress on [001] and [110] wafers. The calculations and experimental data show that low in-plane and large out-of-plane conductivity effective masses and a high density of states in the top band are all important for large hole mobility enhancement. This work suggests longitudinal compressive stress on [001] or [110] wafers and <110> channel direction offers the most favorable band structure for holes. The maximum Si inversion-layer hole mobility enhancement is estimated to be /spl sim/ 4 times higher for uniaxial stress on (100) wafer and /spl sim/ 2 times higher for biaxial stress on (100) wafer and for uniaxial stress on a [110] wafer.     

Study of thinned Si wafer warpage in 3D stacked wafers

3D (three-dimensional) wafer stacking technology has been developed extensively recently. One of the many technical challenges in 3D stacked wafers, and one of the most important, is wafer warpage. Wafer warpage is one of the root causes leading to process and product failures such as delamination, cracking, mechanical stresses, within wafer (WIW) uniformity and even electrical failure. In this study, the wafer warpage of thinned Si wafers in stacked wafers has been evaluated. Si wafer or glass was used as a thick substrate, and Cu or polyimide was used as the bonding material. The top Si wafer in the bonded stack was ground down to 20–100 μm, and wafer curvature was measured. Wafer curvature and how it relates to bonding material, substrate material of the stacked layers, and thickness of thinned Si wafer will be discussed.     

Electrochemical lithiation of silicon with varied crystallographic orientation

The anisotropy of lithium intercalation into the silicon anodes of Li-ion batteries is studied on microstructures having the form of a grid with 0.5-μm-thick vertical walls and on silicon wafers of varied orientation. Electrochemical lithiation is performed at room temperature in the galvanostatic mode. The charging curves of the microstructure and flat Si anodes are examined. Secondary-ion mass spectroscopy is used to determine the distribution of intercalated Li atoms across the wafer thickness. The experimental data are analyzed in terms of the two-phase model in which the lithiation process is limited by the propagation velocity of the front between the amorphous alloy with a high Li content and the crystalline Si substrate. The relationship between the rates of Li intercalation into different crystallographic planes: (110), (111), and (100), is found to be V₁₁₀: V₁₁₁: V₁₀₀ = 3.1: 1.1: 1.0. It is demonstrated that microstructure anodes with (110) walls have the highest cycle life and withstand ~600 cycles when charged and discharged at a rate of 0.36 C.     

Silicon layer transfer using wafer bonding and debonding

Two experiments were performed that demonstrate an extension of the ion-cut layer transfer technique where a polymer is used for planarization and bonding. In the first experiment hydrogen-implanted silicon wafers were deposited with two to four microns low-temperature plasma-enhanced tetraethoxysilane (TEOS). The wafers were then bonded to a second wafer, which had been coated with a spin-on polymer. The bonded pairs were heated to the ion-cut temperature resulting in the transfer of a 400 nm layer silicon. The polymer enabled the bonding of an unprocessed silicon wafer to the as-deposited TEOS with a microsurface roughness larger than 10 nm, while the TEOS provided sufficient stiffness for ion cut. In the second experiment, an intermediate transfer wafer was patterned and vias were etched through the wafer using a 25% tetramethylammonium hydroxide (TMAH) solution and nitride as masking material. The nitride was then stripped using dilute hydrofluoric acid (HF). The transfer wafer was then bonded to an oxidized (100 nm) hydrogen-implanted silicon wafer. After ion-cut annealing a silicon-on-insulator (SOI) wafer was produced on the transfer wafer. The thin silicon layer of the SOI structure was then bonded to a third wafer using a spin-on polymer as the bonding material. The sacrificial oxide layer was then etched away in HF, freeing the thin silicon from the transfer wafer. The result produced a thin silicon-on-polymer structure bonded to the third wafer. These results demonstrate the feasibility of transferring a silicon layer from a wafer to a second intermediate “transfer” or “universal” reusable substrate. The second transfer step allows the thin silicon layer to be subsequently bonded to a potential third device wafer followed by debonding of the transfer wafer creating stacked three-dimensional structures.     

Hybrid-orientation technology (HOT): opportunities and challenges

At the onset of innovative device structures intended to extend the roadmap for silicon CMOS, many techniques have been investigated to improve carrier mobility in silicon MOSFETs. A novel planar silicon CMOS structure, seeking optimized surface orientation, and hence carrier mobilities for both nFETs and pFETs, emerged. Hybrid-orientation technology provides nFETs on (100) surface orientation and pFETs on [110] surface orientation through wafer bonding and silicon selective epitaxy. The fabrication processes and device characteristics are reviewed in this paper.     

(001)InP晶片[110]及[1 0]取向的最新判别法

本文提出了一种判别(001)晶片[110]和[ ]方向的简便方法。将去掉机械划痕的 InP 衬底放入浓 HCl,发现腐蚀出的条形沟方向是和片子的[110]方向一致。并对腐蚀沟的形成做了初步分析。     

Evaluation of four inch diameter VGF-Ge substrates used for manufacturing multi-junction solar cell

Low dislocation density Ge wafers grown by a vertical gradient freeze (VGF) method used for the fabrication of multi-junction photovoltaic cells (MJC) have been studied by a whole wafer scale measurement of the lattice parameter, X-ray rocking curves, etch pit density (EPD), impurities concentration, minority carrier lifetime and residual stress. Impurity content in the VGF-Ge wafers, including that of B, is quite low although B₂O₃ encapsulation is used in the growth process. An obvious difference exists across the whole wafer regarding the distribution of etch pit density, lattice parameter, full width at half maximum (FWHM) of the X-ray rocking curve and residual stress measured by Raman spectra. These are in contrast to a reference Ge substrate wafer grown by the Cz method. The influence of the VGF-Ge substrate on the performance of the MJC is analyzed and evaluated by a comparison of the statistical results of cell parameters.     

A 150%enhancement of PMOSFET mobility using hybrid orientation

正A high-performance PMOSFET based on silicon material of hybrid orientation is obtained.Hybrid orientation wafers,integrated by(100) and(110) crystal orientation,are fabricated using silicon-silicon bonding, chemical mechanical polishing,etching silicon and non-selective expitaxy.A PMOSFET with W/L = 50μm/8μm is also processed,and the measured results show that the drain-source current and peak mobility of the PMOSFET are enhanced by up to 50.7%and 150%at V_(gs) =-15 V and V_(ds) =-0.5 V,respectively.The mobility values are higher than that reported in the literature.     

Temperature measurement of metal-coated silicon wafers bydouble-pass infrared transmission

We report the measurement of the temperature of metal-coated silicon wafers by a double-pass infrared transmission technique. Infrared light incident on the backside of the wafer passes through the wafer, and is re-emitted out the backside after reflecting off the metal surface on the front side of the wafer. The temperature is inferred by the change in the re-emitted signal due to absorption in the wafer. The work has been demonstrated on double-polished wafers from 100°C to 550°C using wavelengths from 1.1 to 1.55 μm. A method for overcoming limitations of the present arrangement for wafers with a rough backside is proposed     

Deposition of the IV–VI films by the hot-wall method on silicon substrates 100 mm in diameter

An experimental installation for the deposition of films of IV–VI compounds by the hot-wall method on silicon substrates 100 mm in diameter is described. The PbTe films on silicon wafers with orientation (100) are obtained and investigated. The PbTe films have a continuous mirror surface and repeat the substrate orientation. The peculiarities of obtaining such films are discussed.     

Fabrication of ultrathin SOI by SIMOX water bonding (SWB)

Ultrathin silicon-on-insulator (SOI) layers of separation by implantation of oxygen (SIMOX) wafers have been transferred onto thermally oxidized silicon wafers by wafer bonding technology. Due to the technical availability and the complementary nature of SIMOX and wafer bonding approaches, SIMOX wafer bonding (SWB) solves some of the respective major difficulties faced by both SIMOX and wafer bonding for device quality ultrathin SOI mass production: the preparation of adequate buried oxide (including its interfaces) in SIMOX and the uniformly thinning one of the bonded wafers to less than 0.1 μm in wafer bonding. The effect of positive charges in the oxide on bondability of ultrathin SOI films and possible applications of SWB will also be outlined.     

Preparation of silicon-on-gallium arsenide wafers for monolithicoptoelectronic integration

A process is described which combines silicon-on-insulator (SOI) and wafer bonding techniques to create thin (≈100 nm) single-crystal silicon layers on oxide coated gallium arsenide wafers for use in optoelectronic integration. Using a GaAs substrate for the integration eliminates the thermal expansion coefficient mismatch problems which have blocked monolithic integration of thick, stress sensitive optoelectronic devices on silicon, without compromising the performance of CMOS circuitry which can be fabricated in very thin, compressively strained silicon layers using SOT techniques     

High-quality large-area MBE HgCdTe/Si

HgCdTe offers significant advantages over other similar semiconductors, which has made it the most widely utilized variable-gap material in infrared (IR) focal plane array (FPA) technology. HgCdTe hybrid FPAs consisting of two-dimensional detector arrays that are hybridized to Si readout circuits (ROIC) are the dominant technology for second-generation infrared systems. However, one of the main limitations of the HgCdTe materials system has been the size of lattice-matched bulk CdZnTe substrates, used for epitaxially grown HgCdTe, which have been limited to 30 cm² in production. This size limitation does not adequately support the increasing demand for larger FPA formats which now require sizes up to 2048×2048, and only a single die can be printed per wafer. Heteroepitaxial Si-based substrates offer a cost-effective technology that can be scaled to large wafer sizes and further offer a thermal-expansion-matched hybrid structure that is suitable for large format FPAs. This paper presents data on molecular-beam epitaxy (MBE)-grown HgCdTe/Si wafers with much improved materials characteristics than previously reported. We will present data on 4- and 6-in diameter HgCdTe both with extremely uniform composition and extremely low defects. Large-diameter HgCdTe/Si with nearly perfect compositional uniformity and ultra low defect density is essential for meeting the demanding specifications of large format FPAs.     

Process-induced stress and microcrack nucleation in GaAs wafers

Breakage of GaAs wafers during device fabrication leads to reduced yield and decreased quality control. Historically, wafer breakage that is not attributable to human or equipment errors has been assumed to be due to poor quality wafers. We present evidence that the probability of breakage during sub-micron GaAs device fabrication is a function of dielectric film edge stress, and not necessarily dependent on the magnitude of a critical flaw in the as-received wafer. X-ray residual stress measurements, x-ray topographic imaging, and three-point bend fracture measurements are used to determine the nature and origin of wafer breakage during those fabrication steps which induce large mechanical or thermal stresses. Our data show that the processing sequences that most influence wafer breakage are SiN passivation deposition and rapid thermal annealing implant activation. These processes are primarily responsible for large residual stresses developed in the near-surface layers of the GaAs substrate. For microelectronic applications, the existence of high film edge stresses nucleates microcracks, which further reduces fracture strength. The combined effects of high residual stress and low fracture strength make SiN passivated wafers more fragile (as compared to SiON passivated wafers), and therefore more likely to break during device processing.     

Assessment of ultra-thin Si wafer thickness in 3D wafer stacking

3D integration with multi-stacked wafers is a promising option to enhance device performance and density beyond traditional device scaling limits. However, to bring wafer stacking into reality, there are many technological challenges to be resolved, and one of those is the problem of uniform Si wafer thinning. For multi-stacked devices, Si wafers must be drastically thinned down to less than 50 μm. Problems associated with such ultra-thin Si wafers range from basic wafer handling to difficulty in accurately assessing the thickness of the thinned wafer across the wafer. In this study, bonded wafer pairs have been prepared with different bonding materials, and the stacks were ground down to about 30 μm. The thickness of the ultra-thin wafers was measured by Fourier transform infrared spectrometry (FTIR) technique, and its stability based on bonding status as well as measuring issues will be discussed.     

The removal of deformed submicron particles from silicon wafers by spin rinse and megasonics

In order to successfully clean particulate contamination from wafer surfaces, it is necessary to understand the adhesion and deformation between the particles and the substrate in contact. The adhesion and removal mechanisms of deformed submicron particles have not been addressed in many previous studies. Submicron polystyrene latex particles (0.1–0.5 μm) were deposited on silicon wafers and removed by spin rinse and megasonic cleanings. Particle rolling is identified as the major removal mechanism for the deformed submicron particles from silicon wafers. Megasonics provides larger streaming velocity because of the extremely thin boundary layer resulting in a larger removal force that is capable of achieving complete removal of contamination particles.