共查询到20条相似文献,搜索用时 15 毫秒
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Nebojsa Jankovic Zhongfu Zhou Steve Batcup Petar Igic 《International Journal of Electronics》2013,100(7):767-779
An advanced sub-circuit model of the punch-trough insulated gate bipolar transistor (PT IGBT) based on the physics of internal device operation has been described in this article. The one-dimensional physical model of low-gain wide-base BJT is employed based on the equivalent non-linear lossy transmission line, whereas a SPICE Level 3 model is used for the diffused MOST part. The influence of voltage dependent drain-to-gate overlapping capacitance and the conductivity modulated base (drain) ohmic resistance are modelled separately. The main advantages of novel PT IGBT model are a small set of model parameters, an easy implementation in SPICE simulator and the high accuracy confirmed by comparing the simulation results with the electrical measurements of test power circuit. 相似文献
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A physically based semiempirical model for electron mobilities of the MOSFET inversion layers that is valid over a large temperature range (77 K⩽T ⩽370 K) is discussed. It is based on a reciprocal sum of three scattering mechanisms, i.e. phonon, Coulomb, and surface roughness scattering, and is explicitly dependent on temperature and transverse electric field. The model is more physically based than other semiempirical models, but has an equivalent number of extracted parameters. It is shown that this model compares more favorably with the experimental data than previous models. The implicit dependencies of the model parameters on oxide charge density and surface roughness are confirmed 相似文献
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A. Balijepalli J. Ervin W. Lepkowski Y. Cao T.J. Thornton 《Microelectronics Journal》2009,40(9):1264-1273
A compact model for the partially depleted (PD) silicon-on-insulator (SOI) metal semiconductor field effect transistor (MESFET) is presented. The absence of a gate-oxide makes the SOI MESFET extremely robust, able to withstand high voltages, and useful for extreme environment electronics. These devices have been fabricated using a standard SOI CMOS process. In contrast to SOI MOSFETs and GaAs MESFETs, the source-substrate voltage has a significant impact on the channel current. In this work a model has been developed that includes the effect of the buried oxide on the performance of the MESFET. The model has been verified for a wide temperature range of −180 to 150 °C. A behavioral model has been included to model the breakdown voltage. The core DC and RF models have been adapted from the commercially available Triquint's Own Model (TOM3) MESFET model. Building from the TOM3 model, a measurement-based approach is used to develop a four-terminal compact model using Verilog-A. The charge-based approach, using S-parameter measurements was used to develop the capacitance model. We also present a voltage reference circuit using two MESFET transistors to verify the model and explore wide temperature range circuit applications. 相似文献
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本文设计了一种简单的一阶温度补偿电流基准源.主要利用电阻的温度系数与阈值电压VTH温度系数相同的特性实现温度补偿原理.该主体电路采用低压共源共栅(即CASCODE)结构,不需要运放,易于补偿.整个电路采用0.5μm标准CM0S工艺,并用HSPICE仿真分析表明该电路在0~100℃范围内且在工艺变化(容差分析)时基准电流变化不超过3.1%. 相似文献
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A compact Ids model with physical drain-conductance (gds) modeling for deep-submicron MOSFETs is formulated based on first-principle momentum-/energy-balance equations, which simultaneously includes the hot-electron and thermoelectric effects in a unified compact form with two fitting parameters and one-step extraction. The model has been verified with 0.18-μm experimental data with good gds prediction. 相似文献
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Ken-ichi ShinkaiAuthor Vitae Masanori HashimotoTakao OnoyeAuthor Vitae 《Integration, the VLSI Journal》2013
This paper proposes a gate-delay model suitable for timing analysis that takes into consideration wide-ranging process–voltage–temperature (PVT) variations. The proposed model translates an output-current fluctuation due to PVT variations into modifications of the output load and input waveform. After translation, any conventional model can compute delay taking into account PVT variations by using the modified output load and reshaped input waveform. Experimental results with 90- and 45-nm technologies demonstrate that the average error of the fall and rise delay estimation in single- and multi-stage gates was approximately 5% on average over a wide range of input slews, output loads, and PVT variations. The proposed model can be used in Monte Carlo STA (static timing analysis) in addition to corner-based timing analysis. It can be also used in statistical STA to calculate the sensitivities of delays to variation parameters on-the-fly even when the nominal operating condition changes as well. 相似文献
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为了对Spice程序下的二极管模型的伏安特性和等效电容受温度变化的影响进行研究,在此以软件Matlab的仿真环境为基础,Spice二极管物理模型D1N4002为研究对象,在仿真软件Matlab中编写程序代码,建立了二极管模型D1N4002的伏安特性和等效电容的函数模型,绘制出不同温度下二极管伏安特性和等效电容的曲线,并结合仿真曲线对由温度变化产生的影响进行分析,得出了温度对二板管模型在反向击穿和正向导通状态下的伏安特性及等效电容有明显的影响这一结论。该研究方法以一个新颖的视角,运用Matlab构造特性函数,以温度为变量,研究了Spice二极管模型的特性,同时也为其他更加复杂的半导体器件特性的研究打下了基础。 相似文献
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底层代码开源的CC2530节点芯片,在煤田火区无线传感器监测大规模组网中更具优势。针对CC2530节点不具有SPI接口的情况,利用USART接口引脚模拟了SPI接口,采用32位MAX31855与K型热电偶的模数转换,通过编写时钟片选、数据传输、时序及主从引脚配置的控制软件,开发了测温范围-40℃~1000℃的高温CC2530无线传感器网络节点。火焰、沸水、冰块的温度测试实验表明,编写的控制软件正确地转换和处理了热电偶的模拟电压量,模拟SPI口稳定地传输数据,为宽范围的温度监测需求提供可选项。 相似文献
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A large signal model for InP/InGaAs double heterojunction bipolar transistors including thermal effects has been reported,which demonstrated good agreements of simulations with measurements.On the basis of the previous model in which the double heterojunction effect,current blocking effect and high current effect in current expression are considered,the effect of bandgap narrowing with temperature has been considered in transport current while a formula for model parameters as a function of temperature has been developed.This model is implemented by Verilog-A and embedded in ADS.The proposed model is verified with DC and large signal measurements. 相似文献
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为了抑制异质栅SOI MOSFET的漏致势垒降低效应,在沟道源端一侧引入了高掺杂Halo结构.通过求解二维电势Poisson方程,为新结构器件建立了全耗尽条件下表面势和阈值电压解析模型,并对其性能改进情况进行了研究.结果表明,新结构器件比传统的异质栅SOI MOSFETs能更有效地抑制漏致势垒降低效应,并进一步提高载流子输运效率.新结构器件的漏致势垒降低效应随着Halo区掺杂浓度的增加而减弱,但随Halo区长度非单调变化.解析模型与数值模拟软件MEDICI所得结果高度吻合. 相似文献
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异质栅非对称Halo SOI MOSFET 总被引:2,自引:1,他引:2
为了抑制异质栅SOI MOSFET的漏致势垒降低效应,在沟道源端一侧引入了高掺杂Halo结构.通过求解二维电势Poisson方程,为新结构器件建立了全耗尽条件下表面势和阈值电压解析模型,并对其性能改进情况进行了研究.结果表明,新结构器件比传统的异质栅SOI MOSFETs能更有效地抑制漏致势垒降低效应,并进一步提高载流子输运效率.新结构器件的漏致势垒降低效应随着Halo区掺杂浓度的增加而减弱,但随Halo区长度非单调变化.解析模型与数值模拟软件MEDICI所得结果高度吻合. 相似文献
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Jian-Song Chen Kornegay K.T. Sei-Hyung Ryu 《Solid-State Circuits, IEEE Journal of》1999,34(2):192-204
In this paper, we present the design and fabrication of a high-temperature silicon carbide CMOS intelligent gate driver circuit intended for high-power switching applications. Using a temperature-insensitive comparator, several functions including overvoltage and undervoltage, as well as short- and open-load detection, are provided, all of which are operational up to 300°C. These integrated circuits are ideally suited for harsh and high-temperature environments such as automotive and aircraft jet engines 相似文献
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Giuseppe Ferri Vincenzo Stornelli 《Analog Integrated Circuits and Signal Processing》2006,47(3):293-301
In this work we present an integrated interface for wide range resistive gas sensors able to heat the sensor resistance through
a constant power heater block at 0°C–350°C operating temperatures. The proposed temperature control system is formed by a
sensor heater (which fixes the sensor temperature at about 200°C), a R/f (or R/T) converter, which converts the resistive value into a period (or frequency), and can be able to reveal about 6 decades variation
(from 10 KΩ up to 10 GΩ), and a digital subsystem that control the whole systems loop. This interface allows high sensibility
and precision and performs good stability in temperature and power supply drift and low power characteristics so it can be
used also in portable applications. Test measurements, performed on the fabricated chip, have shown an excellent agreement
between theoretical expectations and simulation results.
Giuseppe Ferri is an associate professor in Electronics at the Department of Electrical Engineering of L’ Aquila University, Ital. In 1993
he has been a visiting researcher at SGS-Thomson Milano, working in bipolar low-voltage op-amp design. In 1994-95 he has been visiting researcher at KU Leuven working in low-voltage CMOS design in the group of Prof. Sansen. His research activity is actually centred on the analog
design of integrated circuits for portable applications (e.g., sensors and biomedicals) and circuit theory. He is co-author
of a book entitled “Low Voltage, Low Power CMOS Current Conveyors”, Kluwer ed. (2003) and four text-books in Italian on Analogue Microelectronics (2005, 2006). Moreover, he is author and
co-author of 74 papers on international and Italian journals and 123 talks at national and international conferences.
Vincenzo Stornelli was born in Avezzano (AQ), Italy, on May 31, 1980. He received the Electronics Engineering degree (cum laude) in July 2004.
In October 2004 he joined the Department of Electronic Engineering, University of L’Aquila, where he is actually involved
with problems concerning project and design of integrated circuits for RF and sensor applications, CAD modelling, characterization,
and design analysis of active microwave components, circuits, and subsystems. He regularly teaches courses of the European
Computer patent and has regular collaborations with national corporations such as Thales Italia 相似文献
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摘要:本文设计了一款宽电压供电范围、用于神经电信号采集的前端芯片。该芯片主要由前端放大电路、仪表放大器(IA)和循环结构模数转换器(CADC)构成。在不采用分立元件的情况下,前端放大电路采用电容耦合、电容反馈的拓扑结构,结合伪电阻的应用,产生一个小于1Hz的-3dB高通频率截止点。双运算仪表放大器用于进一步提高增益的同时也为后续的模数转换电路提供一个较低的输出阻抗。前端放大电路和仪表放大电路共提供45.8dB的增益,其等效输入参考噪声电压为6.7uV从1Hz~5KHz积分)。放大后的信号被12位采样精度的ADC采样,该ADC最高采样速率为139KS/s,有效位数为8.7位。整个电路在1.34V到3.3V供电范围内消耗的总电流为165uA到 216uA。该芯片采用联华电子公司(UMC)的0.18-um 工艺制造,总面积1.06mm2 。该芯片在仿真生理环境下成功地记录到了神经电信号。 相似文献
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An improved small-signal equivalent circuit of HBT concerning the AC current crowding effect is proposed in this paper.AC current crowding effect is modeled as a parallel RC circuit composed of Cbi and Rbi,with distributed base-collector junction capacitance also taken into account.The intrinsic portion is taken as a whole and extracted directly from the measured S-parameters in the whole frequency range of operation without any special test structures.An HBT device with a 2 × 20 μm2 emitter-area under three different biases were used to demonstrate the extraction and verify the accuracy of the equivalent circuit. 相似文献