一种用于MEMS电容式加速度计的116dB动态范围CMOS读出电路

A high stability in-circuit reprogrammable technique control system for a capacitive MEMS accelerometer is presented. Modulation and demodulation are used to separate the signal from the low frequency noise. A low-noise low-offset charge integrator is employed in this circuit to implement a capacitance-to-voltage converter and minimize the noise and offset. The application-specific integrated circuit （ASIC） is fabricated in a 0.5 /μm one-ploy three-metal CMOS process. The measured results of the proposed circuit show that the noise floor of the ASIC is -116 dBV, the sensitivity of the accelerometer is 66 mV/g with a nonlinearity of 0.5%. The chip occupies 3.5×2.5 mm2 and the current is 3.5 mA.     

Design of vision measurement system of double optical paths with single CCD based on DSP

The design of vision measurement system of double optical paths with single CCD based on the digital signal processor （DSP） is presented. Using TMS320F2812 as the intelligent control unit, the CCD driving circuit, level conversion circuit and CCD output signal data acquisition and processing circuit are designed. By means of plane reflectors, the optical structure of the system is optimized, which reduces errors owing to tilt effect of the measured unit, improves measuring accuracy and makes the system more compact. Double optical paths signal data acquisition with single CCD is demonstrated. In addition, the improved resolution is enhanced up to sub-pixel level by the average polynomial interpolation algorithm.     

Application of Correlated Double Sampling in Space TDICCD Camera

As a sampling technique for CCD output video signal, the correlated double sampling (CDS) technique is described as well as the filtering effects of the CDS technique on the output noise of CCD including the reset noise of CCD, the white noise of output amplifier and 1/f noise. From real application of CDS device TH7982A, it is concluded that the output signal-to-noise ratio of 50 dB for CCD signal can be obtained.     

A 14-bit 40-MHz analog front end for CCD application

A 14-bit, 40-MHz analog front end (AFE) for CCD scanners is analyzed and designed. The proposed system incorporates a digitally controlled wideband variable gain amplifier (VGA) with nearly 42 dB gain range, a correlated double sampler (CDS) with programmable gain functionality, a 14-bit analog-to-digital converter and a programmable timing core. To achieve the maximum dynamic range, the VGA proposed here can linearly amplify the input signal in a gain range from -1.08 to 41.06 dB in 6.02 dB step with a constant bandwidth. A novel CDS takes image information out of noise, and further amplifies the signal accurately in a gain range from 0 to 18 dB in 0.035 dB step. A 14-bit ADC is adopted to quantify the analog signal with optimization in power and linearity. An internal timing core can provide flexible timing for CCD arrays, CDS and ADC. The proposed AFE was fabricated in SMIC 0.18 μm CMOS process. The whole circuit occupied an active area of 2.8×4.8 mm² and consumed 360 mW. When the frequency of input signal is 6.069 MHz, and the sampling frequency is 40 MHz, the signal to noise and distortion (SNDR) is 70.3 dB, the effective number of bits is 11.39 bit.     

97dB动态范围、带温度补偿的MEMS电容传感器读出电路

This paper presents a charge-sensitive-amplifier(CSA)based readout circuit for capacitive microelectro-mechanical-system(MEMS)sensors.A continuous-time(CT)readout structure using the chopper technique is adopted to cancel the low frequency noise and improve the resolution of the readout circuits.An operational trans-conductance amplifier(OTA)structure with an auxiliary common-mode-feedback-OTA is proposed in the fully differential CSA to suppress the chopper modulation induced disturbance at the OTA input terminal.An analog temperature compensation method is proposed,which adjusts the chopper signal amplitude with temperature variation to compensate the temperature drift of the CSA readout sensitivity.The chip is designed and implemented in a 0.35 m CMOS process and is 2.1 2.1 mm2in area.The measurement shows that the readout circuitachieves0.9aF/√Hz capacitive resolution,97dBd ynamic range in 100Hz signal bandwidth,and 0.8mV/fF sensitivity with a temperature drift of 35 ppm/℃ after optimized compensation.     

High performance QVCO design with series coupling in CMOS technology

A high performance quadrature voltage-controlled oscillator（QVCO） is presented.It has been fabricated in SMIC 0.18μm CMOS technology with top thick metal.The proposed QVCO employed cascade serial coupling for in phase and quadrature phase signal generation.Source degeneration capacitance is added to the NMOS differential pair to suppress their flicker noise from up-conversion to close in phase noise.A dedicated low noise and high power supply rejection low drop out regulator is used to supply this QVCO.The measured phase noise of the proposed QVCO achieves phase noise of-123.3 dBc/Hz at an offset frequency of 1 MHz from the carrier of 4.78 GHz,while the QVCO core circuit and LDO draw 6 mA from a 1.8 V supply.The QVCO can operate from 4.09 to 4.87 GHz（17.5%）.Measured tuning gain of the QVCO(K_vco) spans from 44.5 to 66.7 MHz/V.The chip area excluding the pads and ESD protection circuit is 0.41 mm².     

一种应用于高清视频模拟前端的多功能开关电容可编程增益放大器

A multifunctional programmable gain amplifier(PGA) that provides gain and offset adjusting abilities for high-definition video analog front-ends(AFE) is presented. With a switched-capacitor structure, the PGA also acts as a sample and holder of the analog-to-digital converter(ADC) in the AFE to reduce the power consumption and chip area of the whole AFE. Furthermore, the PGA converts the single-ended video signal into differential signal for the following ADC to reject common-mode noise and interferences. The 9-bit digital-to-analog converter(DAC) for gain and offset adjusting is embedded into the switched capacitor networks of the PGA. A video AFE integrated circuit based on the proposed PGA is fabricated in a 0.18- m process. Simulation and measurement results show that the PGA achieves a gain control range of 0.90 to 2.34 and an offset control range of –220 to220 mV while consuming 10.1 mA from a 1.8 V power supply.     

2.5 Gb／s 16：1 MUX IC Design with CMOS

A low--power and high--speed 16.-1 MUX IC designed for optical fiber communication based on TSMC 0.25μm CMOS technology is presented. A tree—type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak—to—peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8mm^2.     

一种应用于流水线ADC的14-bit 50MS/s 采样保持电路

A high performance sample-and-hold （S/H） circuit used in a pipelined analog-to-digital converter （ADC） is presented. Capacitor flip-around architecture is used in this S/H circuit with a novel gain-boosted differential folded cascode operational transconductance amplifier. A double-bootstrapped switch is designed to improve the performance of the circuit. The circuit is implemented using a 0.18 μm 1P6M CMOS process. Measurement results show that the effective number of bits is 14.03 bits, the spurious free dynamic range is 94.62 dB, the signal to noise and distortion ratio is 86.28 dB, and the total harmonic distortion is -91.84 dB for a 5 MHz input signal with 50 MS/s sampling rate. A pipeline ADC with the designed S/H circuit has been implemented.     

2.5 Gb/s 16∶1 MUX IC Design with CMOS

A low-power and high-speed 16:1 MUX IC designed for Optical fiber communication based on TSMC 0.25 μm CMOS technology is represented. A tree-type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak-to-peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is (1.8) mm~(2).     

应用于海洋观测的TDI-CCD驱动电路的设计

面阵CCD及线阵CCD不能胜任海洋目标观测的要求,选用具有高信噪比高灵敏度的时间延迟积分CCD(Time delay integration CCD, TDI-CCD)作为 探测器并实现其驱动电路。在图像采集过程中,TDI-CCD探测器使用两个读取端口输出。 该探测器驱动电路产 生TDI-CCD和A/D的驱动时序。CCD的模拟输出信号被A/D采样,转换成可被计算机识别 的数字信号。采用FPGA作为主控芯片,产生驱动时序,接收被A/D转换过的数字信号, 并发送图像至计算机。利用相关双采样(Correlated double sampling, CDS)技术滤除TDI-CCD模 拟输出信号的相关噪声,提高信号的信噪比。现场可编程门阵列(Field programmable gate array, FPGA)代码在ISE14.7下进行仿真,实验表明,研制的TDI-CCD驱动电路能够产生CCD要求的驱动时序。     

多通道TDICCD卫星遥感相机图像噪声分析与处理

为了解决多路时间延迟积分电荷耦合器件(TDICCD)拼接遥感相机成像的噪声问题,提高载荷焦面电箱的成像信噪比和成像质量,通过分析噪声现象,发现多路TDICCD成像噪声的主要原因有两个:一是多通道TDICCD未能实现同时刻开启成像,使得成像电路电源出现高频纹波噪声且多通道噪声相混叠,这样对各通道CCD模拟信号造成干扰;二是电路中的DC-DC电源开关噪声扰动影响了CCD有效视频信号的采集。从工程研制实际出发,采取CCD通道之间共用统一的系统时钟,相同系统复位等措施对多TDICCD成像电路系统进行改进,抑制通道间成像串扰的发生,通过对主要干扰源DC-DC电源进行滤波处理与TDICCD端多点接地等方式,抑制电源噪声对TDICCD成像的干扰。对改进后的多通道TDICCD成像电路系统进行成像和信噪比测试。实验结果表明,采取的措施有效地去除了TDICCD成像噪声,相机信噪比提高了2 dB,且外场成像质量高,可满足实际工程的需求。     

大幅度CCD输出信号降噪的相关双取样电路

电荷耦合器件(CCD)的输出信号构成复杂,包含有典型的KTC、1/f等类型的噪声,需要进行专门处理后才能获得与入射光信号相对应的高信噪比信号。文章针对具有较大幅度的CCD输出信号,采用宽电压工作的独立运放满足幅度较大的信号处理要求;通过在同一个运算放大器上实现噪声保持及信号采样的形式,消除了不同通道增益差异对信号的影响,获得了较高线性度的信号处理效果;同时结合CCD驱动器的设计,获取相关双取样技术所需的采样及保持脉冲信号,增强了采样与CCD输出信号间的关联程度,从而进一步提高了相关双取样技术消除CCD噪声的效果。采用这种信号处理电路后,将原来噪声处理的水平从约22 mV提高到了约1 mV,并且在一种精密的位移测量系统中得到应用,最后就具体电路设计的难点及注意事项进行了阐述。     

4路长积分时间CCD成像电路的设计与实现

基于CCD47-20和CCD55-30探测器设计了一种4路探测器成像电路。由于积分时间长,该系统可以在弱光条件下实现高灵敏度成像。建立了探测器的驱动电路模型,分析了CCD探测器对驱动的要求,以选择合适的驱动芯片;在分析探测器噪声特性的基础上,通过相关双采样法和合理的滤波器设置抑制了电路噪声。针对4路探测器信号处理电路之间的串扰问题进行了分析和对比,为合理的PCB布局布线提供了参考。该成像电路与商用镜头搭配使用后已成功获取了微光条件下的低噪声外景图像。     

行间转移型面阵CCD图像采集系统的研究

详细介绍了一种行问转移型面阵CCD的图像采集系统的原理及硬件组成。设计了基于复杂可编程逻辑器件（CPLD）的CCD驱动时序发生器及上电顺序可控的智能电源,采用视频处理专用集成芯片对视频信号进行去噪量化。测试结果表明该系统实现了对面阵CCD信号快速而准确地采集,其硬件电路结构简单、调试灵活、通用可靠,具有一定的实用价值和应用前景。     

CCD输出信号的低噪声处理电路研究

本文针对电荷耦合器件（CCD）输出信号需要的低噪声处理要求研究了一种高增益、低噪声的信号处理电路,指出了电路的设计难点及注意事项。     

CCD视频信号的预处理电路设计与仿真

分析了CCD图像传感器件视频信号的读出过程和信号特点,针对信号特点,设计了CCD视频信号直流分量的去除、低通滤波放大及复位噪声消除等预处理电路,实现了CCD输出信号由混有噪声的微弱光感生电压向标准信号电压的转换,利用EDA软件prote199se进行仿真测试,获得了满意的结果．     

红外CCD信号处理电路的设计

由于红外CCD的输出为高背景、宽动态范围的信号,所以在该信号的处理电路中,去除直流高背景和自动增益对于滤除背景噪声、提取目标信号必不可少．通过分析红外CCD信号处理电路的设计要求,介绍了应用于该信号处理的几种常用电路的设计方法．最后,着重阐述了基于CPLD(复杂可编程逻辑器件)和VSP3010的CCD信号处理电路的一体化设计方法．     

A 2-million-pixel CCD image sensor overlaid with an amorphoussilicon photoconversion layer

A highly sensitive 2-million-pixel high-definition charge-coupled device (CCD) image sensor was developed that features an overlaid amorphous silicon photoconversion layer on an interline transfer-type CCD scanner. The device is adapted to the 16:9 aspect ratio. 1125 scanning lines and 2:1 interlace high-definition TV system. A dual-channel horizontal CCD register is used to reduce the operating frequency to one half of the 74.25-MHz readout frequency. A horizontal period signal storage memory (1H line memory) is provided between the vertical CCD register and the horizontal CCD register to provide the signal distribution from the vertical CCD to the horizontal CCD register during the 3.77-μs short horizontal blanking interval. This device realized a 1000 TV line horizontal limiting resolution 210 nA/1x high sensitivity. Total random noise was found to be 52 electrons RMS and a 72-dB dynamic range was achieved     

基于电荷耦合器件的雷达视频积累电路

电荷耦合器件是一种发展前景良好的金属氧化物半导体（MOS）集成电路。该电路广泛应用于彩色成像、信号处理等相关领域。文介绍一种用CCD321型电荷藕合器件设计和实现的脉冲雷达视频积累电路,目的在于探讨使用该器件实现雷达视频积累的可行性和实际效果。实践证明,使用该器件实现雷达信号积累能有效地提高雷达的信噪比,改善雷达的检测能力,达到增加雷达的发现概率和探测距离的目的。经测试,使用该电路可使雷达信噪比可提高3．5dB。