反应溅射的TaN金属栅的材料性质和有效功函数研究

本文研究了反应溅射的TaN金属栅的电阻,晶体结构和有效功函数(EWF). 原始生长的TaN薄膜具有fcc 结构。经过900 oC后金属退火（PMA）,反应溅射时的氮气流量大于6.5 sccm的TaN仍保持fcc 结构,而反应溅射时的氮气流量小于6.25 sccm的TaN显示了微结构的变化。接着测量了用TaN作为电极的SiO2 和HfO2 栅平带电压随TaN反应溅射时氮气流量的变化。结果显示在介电质和TaN的界面会形成一个电偶矩,它对EWF的贡献会随TaN中的Ta/N比、介质层的性质和 PMA条件不同而变化。     

TiN/TaN 厚度变化对nMOSCAP栅叠层有效功函数的影响

We evaluated the TiN/TaN/TiA1 triple-layer to modulate the effective work function （EWF） of a metal gate stack for the n-type metal-oxide-semiconductor （NMOS） devices application by varying the TiN/TaN thickness. In this paper, the effective work function of EWF ranges from 4.22 to 4.56 eV with different thicknesses of TiN and TaN. The thinner TiN and/or thinner in situ TaN capping, the closer to conduction band of silicon the EWF is, which is appropriate for 2-D planar NMOS. Mid-gap work function behavior is observed with thicker TiN, thicker in situ TaN capping, indicating a strong potential candidate of metal gate material for replacement gate processed three-dimensional devices such as FIN shaped field effect transistors. The physical understandings of the sensitivity of EWF to TiN and TaN thickness are proposed. The thicker TiN prevents the A1 diffusion then induces the EWF to shift to mid-gap. However, the TaN plays a different role in effective work function tuning from TiN, due to the Ta-O dipoles formed at the interface between the metal gate and the high-k layer.     

Top-TiN生长条件及TaN厚度对MOSCAP栅叠层有效功函数的影响

我们引入TaN/TiAl/top-TiN三层结构,通过变化TaN的厚度及top-TiN的生长条件来调节TiN-based金属栅叠层的有效功函数。实验结果显示：较薄的TaN和PVD-process生长的top-TiN组合可以得到较小的有效功函数(EWF),而较厚的TaN和ALD-process生长的top-TiN组合可以得到较大的有效功函数(EWF),文中EWF有从4.25eV to 4.56eV的变化。同时文中也给出了TaN厚度及top-TiN的生长条件调节有效功函数(EWF)的物理解释。与PVD-process在室温条件下生长TiN相比,ALD-process TiN是在400 ℃条件下生长的,400 ℃ ALD-process TiN 可以为整个工艺过程提供更多的热预算,从而促进更多的Al原子扩散进入top-TiN,导致扩散进入到bottom-TiN的Al原子数量减少。另外,厚的TaN也会阻止Al原子进入bottom-TiN。这些因素都减少了bottom-TiN中Al原子的数量,减弱了Al原子对有效功函数的调节作用,从而引起EWF的增加。     

Modulation of the effective work function of TiN metal gate for PMOS application

It is important to find a way to modulate the work function of TiN metal gate towards the valence band edge of Si,which can meet the lower threshold voltage requirement of p-type metal-oxide-semiconductor（MOS） transistor.In this work,effects of TiN thickness,post-deposition annealing（PDA）,oxygen incorporation and N concentration variation on the work function of TiN metal gate in MOS structures are systematically investigated. It can be found that the work function positively shifts at the initial stage as the thickness of the TiN layer increases and stabilizes at such a thickness.PDA at N₂ ambience with a trace of O₂ can also cause a positive shift in the work function of TiN metal gate.The same tendency can be observed when oxygen is incorporated into TiN.Finally, increasing the N concentration in TiN can also positively shift the work function.All these measures are effective in modulating the TiN metal gate so that it is more suitable for PMOS application.     

针对PMOS应用的TiN金属栅功函数调节

PMOS管需要金属栅的功函数接近硅的价带边,所以寻找到合适的方法调节TiN的功函数使之正向移动是金属栅工程的重点,也是难点。本文详细研究了TiN金属栅的厚度,栅介质沉积后退火,氧引入,以及N含量变化对TiN功函数的影响。发现随着TiN的厚度变厚,功函数会正向移动,但是在某一个厚度会达到饱和,另外,在少量氧气氛围下的栅介质沉积后退火,也能使功函数正向移动,而在TiN中引入氧元素,以及增大N的含量都会使TiN的功函数正向漂移。以上所述方法都能有效的调节TiN的功函数来适应PMOS的需要。     

Oxygen incorporation in TiN for metal gate work function tuning with a replacement gate integration approach

In this study, we used oxygen to increase the work function of a TiN gated stack. To prevent the EOT growth associated with oxygen incorporation, we proposed a novel replacement gate flow, where oxygen incorporation by O₂ anneal on a thin TiN layer was performed after dopant activation. With this novel flow, a maximum work function tuning range of ∼0.32 eV was achieved without significant EOT penalty, making it attractive for p-type metal gate integration.     

一种单材料双功函数栅MOSFET解析模型

An analytical surface potential model for the single material double work function gate(SMDWG) MOSFET is developed based on the exact resultant solution of the two-dimensional Poisson equation. The model includes the effects of drain biases, gate oxide thickness, different combinations of S-gate and D-gate length and values of substrate doping concentration. More attention has been paid to seeking to explain the attributes of the SMDWG MOSFET, such as suppressing drain-induced barrier lowering(DIBL), accelerating carrier drift velocity and device speed. The model is verified by comparison to the simulated results using the device simulator MEDICI. The accuracy of the results obtained using our analytical model is verified using numerical simulations. The model not only offers the physical insight into device physics but also provides the basic designing guideline for the device.     

通过Al掺杂调节TiN金属栅功函数

The effect of Al incorporation on the effective work function(EWF) of TiN metal gate was systematically investigated.Metal-oxide-semiconductor(MOS) capacitors with W/TiN/Al/TiN gate stacks were used to fulfill this purpose.Different thickness ratios of Al to TiN and different post metal annealing(PMA) conditions were employed.Significant shift of work function towards to Si conduction band was observed,which was suitable for NMOS and the magnitude of shift depends on the processing conditions.     

Fermi-level pinning induced thermal instability in the effective work function of TaN in TaN/SiO/sub 2/ gate stack

In this letter, we demonstrate for the first time that the Fermi-level pinning caused by the formation of Ta(N)-Si bonds at the TaN/SiO/sub 2/ interface is responsible for the thermal instability of the effective work function of TaN in TaN/SiO/sub 2/ devices after high temperature rapid thermal annealing (RTA). Because of weak charge transfer between Hf and Ta(N) and hence negligible pinning effect at the TaN/HfO/sub 2/ interface, the effective work function of TaN is significantly more thermally stable on HfO/sub 2/ than on SiO/sub 2/ dielectric during RTA. This finding provides a guideline for the work function tuning and the integration of metal gate with high-/spl kappa/ dielectric for advanced CMOS devices.     

亚20nm节点后栅工艺体硅FinFET器件参数优化研究

文章研究了亚 20nm 节点后栅工艺体硅 FinFET PMOS 器件制作过程中一系列工艺参数对器件微缩的影响。实验结果表明细且陡的梯形Fin结构有更好的性能。文章针对穿通阻挡层（PTSL） 和轻掺杂源漏扩散区 （SDE）的注入条件也进行了仔细地优化。SDE之后没有热退火过程的器件由于在源漏退火之后有更好的晶格再生因而拥有更大的驱动电流。带边功函数器件能够改善短沟道效应,而带中功函数具有更大的驱动电流。器件在微缩过程中针对金属栅的有效功函数需要折衷选择。     

Selective wet etch of a TaN metal gate with an amorphous-silicon hard mask

The appropriate wet etch process for the selective removal of TaN on the HfSiON dielectric with an amorphous-silicon(a-Si) hardmask is presented.SCI(NH_4OH:H_2O_2:H_2O),which can achieve reasonable etch rates for metal gates and very high selectivity to high-k dielectrics and hardmask materials,is chosen as the TaN etchant. Compared with the photoresist mask and the tetraethyl orthosilicate(TEOS) hardmask,the a-Si hardmask is a better choice to achieve selective removal of TaN on the HfSiON dielectric be...     

先进CMOS器件中poly-Si/TaN/HfSiON栅结构的干法刻蚀研究

研究了先进CMOS器件中poly-Si/TaN/HfSiON栅结构的干法刻蚀工艺。对于poly-Si/TaN/HfSiON栅结构的刻蚀,我们采用的策略是对栅叠层中的每一层都进行高选择比地、陡直地刻蚀。首先,对于栅结构中poly-Si的刻蚀,开发了一种三步的等离子体刻蚀工艺,不仅得到了陡直的poly-Si刻蚀剖面而且该刻蚀可以可靠地停止在TaN金属栅上。然后,为了得到陡直的TaN刻蚀剖面,研究了多种BCl3基刻蚀气体对TaN金属栅的刻蚀,发现BCl3/Cl2/O2/Ar等离子体是合适的选择。而且,考虑到Cl2对Si衬底几乎没有选择比,采用优化的BCl3/Cl2/O2/Ar等离子体陡直地刻蚀掉TaN金属栅以后,我们采用BCl3/Ar等离子体刻蚀HfSiON高K介质,改善对Si衬底的选择比。最后,采用这些新的刻蚀工艺,成功地实现了poly-Si/TaN/HfSiON栅结构的刻蚀,该刻蚀不仅得到了陡直的刻蚀剖面且对Si衬底几乎没有损失。     

Dry etching of poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor devices

A novel dry etching process of a poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor（CMOS） devices is investigated.Our strategy to process a poly-Si/TaN/HfSiON gate stack is that each layer of gate stack is selectively etched with a vertical profile.First,a three-step plasma etching process is developed to get a vertical poly-Si profile and a reliable etch-stop on a TaN metal gate.Then different BCl₃-based plasmas are applied to etch the TaN metal gate and find that BCl₃/Cl₂/O₂/Ar plasma is a suitable choice to get a vertical TaN profile.Moreover,considering that Cl₂ almost has no selectivity to Si substrate, BCl₃/Ar plasma is applied to etch HfSiON dielectric to improve the selectivity to Si substrate after the TaN metal gate is vertically etched off by the optimized BCl₃/Cl₂/O₂/Ar plasma.Finally,we have succeeded in etching a poly-Si/TaN/HfSiON stack with a vertical profile and almost no Si loss utilizing these new etching technologies.     

Annealing effect on the metal gate effective work function modulation for the Al/TiN/SiO2/p-Si structure

In this work, the thermal annealing effect on the metal gate effective work function (EWF) modulation for the Al/TiN/SiO₂/p-Si(1 0 0) structure was investigated. Compared with the sample of TiN/SiO₂/p-Si(1 0 0) structure, for the sample additionally capped with Al the flat band voltage has a very obvious shift as large as 0.54 V to the negative direction after forming gas annealing. It is also revealed that the thermal budget can effectively influence both the EWF of the gate electrode and the thickness of the gate dielectric layer when a post annealing at 600 °C with different soak times was applied to the samples with Al cap. Material characterization indicates that the diffusion of Al and the formation of Al oxide during annealing should be responsible for all the phenomena. The interface trap density Dit calculated from the high-frequency C-V and the laser-assisted high-frequency C-V curves show that the introduction of Al does not cause reliability problem in the Al/TiN/SiO₂/p-Si structure.     

DC and analog/RF performance optimisation of source pocket dual work function TFET

We investigate a systematic study of source pocket tunnel field-effect transistor (SP TFET) with dual work function of single gate material by using uniform and Gaussian doping profile in the drain region for ultra-low power high frequency high speed applications. For this, a n⁺ doped region is created near the source/channel junction to decrease the depletion width results in improvement of ON-state current. However, the dual work function of the double gate is used for enhancement of the device performance in terms of DC and analog/RF parameters. Further, to improve the high frequency performance of the device, Gaussian doping profile is considered in the drain region with different characteristic lengths which decreases the gate to drain capacitance and leads to drastic improvement in analog/RF figures of merit. Furthermore, the optimisation is performed with different concentrations for uniform and Gaussian drain doping profile and for various sectional length of lower work function of the gate electrode. Finally, the effect of temperature variation on the device performance is demonstrated.     

The effect of oxygen in Ru gate electrode on effective work function of Ru/HfO2 stack structure

Effective work function (φ_m,eff) values of Ru gate electrode on SiO₂ and HfO₂ MOS capacitors were carefully examined and discussed from the viewpoint of an effect of oxygen incorporation in Ru gate electrode on φ_m,eff. Annealing at 400 °C in the reduction (3%H₂) and the oxidation (1%O₂) ambient resulted in similar changes in the φ_m,eff of Ru/HfO₂/SiO₂ and Ru/SiO₂ MOS capacitors. Furthermore, the Ru gate MOS capacitor after annealing in the oxidation condition have shown almost the same φ_m,eff value to that of RuO₂ gate MOS capacitors. The oxygen concentration in the Ru/HfO₂ interface after annealing in oxidizing atmosphere is approximately one order of magnitude higher than that after annealing in reducing atmosphere as confirmed by secondary ion mass spectroscopy analysis. Furthermore, the higher oxygen concentration at the Ru/dielectric interface leads to the higher φ_m,eff value, regardless of SiO₂ or HfO₂ dielectrics. This indicates that φ_m,eff of Ru gate MOS capacitor is dominantly determined by the oxygen concentration at the Ru/dielectric layer interface rather than the dipoles originated from the oxygen vacancy in HfO₂.     

Mechanisms of temperature dependence of threshold voltage in high-k/metal gate transistors with different TiN thicknesses

The change in temperature coefficient of the threshold voltage (=dV_th/dT) for poly-Si/TiN/high-k gate insulator metal–oxide–semiconductor field-effect transistors (MOSFETs) was systematically investigated with respect to various TiN thicknesses for both n- and p-channel MOSFETs. With increasing TiN thickness, dV_th/dT shifts towards negative values for both n- and p-MOSFETs. A mechanism that changes dV_th/dT, depending on TiN thickness is proposed. The main origins are the work function of TiN (Φ_TiN) and its temperature coefficient (dΦ_TiN/dT). These are revealed to change when decreasing the thickness of the TiN layer, because the crystallinity of the TiN layer is degraded for thinner films, which was confirmed by ultraviolet photoelectron spectroscopy (UPS), transmission electron microscopy (TEM) and X-ray diffraction (XRD).     

CMOS传输门工作特性的Multisim分析

针对CMOS传输门工作特性的实验验证,提出了在计算机上应用Multisim仿真软件仿真CMOS传输门传输特性的方法,即用Multisim软件中的函数发生器提供正弦信号、三角信号和脉冲数字信号,用虚拟仪器中的双踪示波器显示输入信号、输出信号的波形。特点是直观形象地描述了CMOS传输门的功能和工作特性、解决了CMOS传输门工作波形无法用电子实验仪器进行分析验证的问题。     

Changes in effective work function of HfxRu1−x alloy gate electrode

Effective work function (?_m,eff) values of Hf_x Ru_1−x alloy gate electrodes on SiO₂ metal-oxide-semiconductor (MOS) capacitors were carefully examined to assess whether the ?_m,eff was determined by the crystalline structure or the composition of the Hf_xRu_1−x alloy. X-ray diffraction results indicated that the crystalline structures of Hf_xRu_1−x alloy were divided into hexagonal-Ru, cubic-HfRu or hexagonal-Hf with the increase of Hf content. The ?_m,eff values could be controlled continuously from 4.6 to 4.0 eV by changing the Hf content. The experimental ?_m,eff value showed a good agreement with theoretical results considering the compositional ratio of pure Hf and Ru. These results suggest that the ?_m,eff of Hf_xRu_1−x alloy gates on SiO₂ MOS capacitors is dominantly determined by the Hf_xRu_1−x composition rather than the crystalline structure.     

The fabrication and dry etching of poly-Si/TaN/Mo gate stack in the metal inserted poly-Si stack structure

The Mo-based metal inserted poly-Si stack (MIPS) structure is an appropriate choice for metal gate and high-k integration in sub-45 nm gate-first CMOS device. A novel metal nitride layer of TaN or AlN with high thermal stability has been introduced between Mo and poly-Si as a barrier material to avoid any reaction of Mo during poly-Si deposition. After Mo-based MIPS structure is successfully prepared, dry etching of poly-Si/TaN/Mo gate stack is studied in detail. The three-step plasma etching using the Cl₂/HBr chemistry without soft landing step has been developed to attain a vertical poly-Si profile and a reliable etch-stop on the TaN/Mo metal gate. For the etching of TaN/Mo gate stack, two methods using BCl₃/Cl₂/O₂/Ar plasma are presented to get both vertical profile and smooth etched surface, and they are critical to get high selectivity to high-k dielectric and Si substrate. In addition, adding a little SF₆ to the BCl₃/O₂/Ar plasma under the optimized conditions is also found to be effective to smoothly etch the TaN/Mo gate stack with vertical profile.