Gate Current Modeling and Optimal Design of Nanoscale Non-Overlapped Gate to Source/Drain MOSFET

In this paper, novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behaviour of novel MOSFET structure has been investigated with help of compact analytical model and Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. It is found that optimal Source/Drain-to-Gate Non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and DIBL characteristic. It is concluded that this structure solves the problem of high leakage current without introducing the extra series resistance.     

Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

In this paper TCAD-based simulation of a novel insulated shallow extension (ISE) cylindrical gate all around (CGAA) Schottky barrier (SB) MOSFET has been reported,to eliminate the suicidal ambipolar behavior (bias-dependent OFF state leakage current) of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions.This novel structure offers low barrier height at the source and offers high ON-state current.The ION/IoFF of ISE-CGAA-SB-MOS-FET increases by 1177 times and offers steeper subthreshold slope (～60 mV/decade).However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate,dual metal gate,single metal gate with ISE,and dual metal gate with ISE has been presented.The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design.The numerical simulation is performed using the ATLAS-3D device simulator.     

A high power MOSFET with a vertical drain electrode and a meshed gate structure

A MOSFET with a maximum power of 200 W in a 5/spl times/5 mm/SUP 2/ chip which exhibits 20-A current, 3000-millimho transconductance and 100-V breakdown voltage has been developed. The features of the device structure are a vertical drain electrode which makes it possible to use most of the surface area for the source electrode, and a meshed gate structure which realizes an increase in the channel width per unit area. The p-channel device with an offset gate structure was fabricated from an n on p/SUP +/ epitaxial wafer by using polysilicon gate and ion implantation processes. The device can be operated stably at ambient temperatures up to 180/spl deg/C. While the bipolar transistor is a suitable power device in the low voltage region, the MOSFET looks more promising in the high voltage region than the V-FET and the bipolar transistor.     

Design and Fabrication of Asymmetric MOSFETs Using a Novel Self-Aligned Structure

A novel asymmetric MOSFET with no lightly doped drain on the source side is simulated on bulk Si using a device simulator (SILVACO). To overcome the problems of the conventional asymmetric process, a novel asymmetric MOSFET using a mesa structure and a sidewall spacer gate is proposed, and it provides a self-alignment process, aggressive scaling, and better uniformity. First of all, we have compared the simulated characteristics of the asymmetric and symmetric MOSFETs. Basically, both asymmetric and symmetric MOSFETs have an n-type channel and the same physical parameters. Compared with the symmetric MOSFET, the asymmetric MOSFET shows better device performance. Moreover, we have successfully fabricated 50-nm asymmetric NMOSFETs based on simulation results and investigated its operation and characteristics.     

Submicrometer salicide CMOS devices with self-aligned shallow/deepjunctions

The use of triple-layer oxide/nitride/PETEOS (plasma-enhanced TEOS) gate spacer, CMOS (T-MOS) structure to form shallow/deep junctions with the deep junction self-aligned to the silicide layer on the source/drain area of submicrometer CMOS devices is discussed. Due to the disposable PETEOS spacer layer, only two masks (one for each channel) are needed to form this source/drain junction signature. A T-MOS structure of 0.5-μm physical gate length has been demonstrated with good device characteristics and ideal junction leakage properties. This T-MOS process, with its moderated doped drain (MDD) structure, is a promising device choice for deep-submicrometer CMOS devices     

Full quantum simulation study of a nano tri-material double gate silicon-on-insulator MOSFET

We present 2D full quantum simulation based on the self-consistent solution of 2D Poisson–Schrödinger equations, within the nonequilibrium Green’s function formalism, for a novel multiple region silicon-on-insulator (SOI) MOSFET device architecture – tri-material double gate (TMDG) SOI MOSFET. This new structure has three materials with different work functions in the front gate, which show reduced short-channel effects such as the drain-induced barrier lowering and subthreshold swing, because of a step function of the potential in the channel region that ensures the screening of the drain potential variation by the gate near the drain. Also, the quantum simulations show the new structure significantly decreases leakage current and drain conductance and increases on–off current ratio and voltage gain as compared to conventional and dual material DG SOI MOSFET.     

Gate isolation after cobalt suicide processing

MOSFET test structures have been prepared with self-aligned suicide (“salicide”) contacts formed by reaction with a cobalt film. This communication describes studies of gate to source/drain leakage in several cobalt salicide lots. Electrical tests establish that the leakage occurs across the oxide spacers. Leakage contour maps resemble dry etching patterns. A mild oxidation treatment following the cobalt stripping etch reduces leakage currents. Cross sectional transmission electron microscopy reveals cobalt remnants on the spacer surfaces in the leaky samples. These and other observations lead to the conclusion that the leakage paths contain both residual cobalt and cobalt silicide, and that the latter originates from silicon deposited on the spacers during pre-metal sputter etching.     

一种新的部分耗尽SOI器件BTS结构

提出了一种新的部分耗尽SOI体接触技术,与其它体接触技术相比,该方法可以有效抑制SOI器件的浮体效应。形成多晶硅栅之前在源区进行大剂量P＋杂质注入,然后形成非对称源区浅结结构。然后生长硅化物电极,厚的硅化物穿透源区浅结与下面高浓度的体区形成欧姆接触。二维器件模拟表明该结构可以有效降低强反型区体区电势,从而抑制了浮体效应。     

A self-aligned elevated source/drain MOSFET

An advanced elevated source/drain CMOS process which features self-aligned lightly-doped drain (LDD) and channel implantation is described. Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new structure provides self-alignment of the LDD regions with the heavily doped channel regions to avoid dopant compensation effects. This process employs a single selective silicon deposition step to define both the epitaxial source/drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source/drain CMOS processes, the final MOSFET structure provides self-alignment of the LDD regions with the heavily doped channel regions. Salicidation is performed after selective silicon deposition to provide low sheet resistances for the source/drain and gate regions. Small-geometry NMOS and PMOS devices have been fabricated which display excellent short channel behavior     

A novel high-performance asymmetric hetero-doped S/D high-voltage MOSFET

A novel high-voltage MOSFET structure, using a simple yet effective concept of an asymmetric hetero-doped source/drain (S/D) is proposed. The asymmetric hetero-doped S/D reduces the on-state resistance of the transistor due to the high doping used for device drain drift, provides excellent ruggedness for parasitic NPN turned-on due to a minimized n/sup +/ source spacer, and also raises the device breakdown voltage due to charge compensation in the composite drain drift region. Therefore, the asymmetric hetero-doped S/D structure allows the high voltage MOSFET to have a high current handling capability with a small device size. This in turn causes the R (sp, on) to be low, leading to high performance for the power device when used in a power integrated circuit. Measured results show that a 24-V breakdown voltage new device with a low-cost two-layer metal (Al) back-end achieves very low R (sp, on) of 0.166 m/spl Omega//spl middot/cm/sup 2/. Furthermore, the new device with a 65-V high-side capability achieves good isolation performance even when switching S/D to -20 V and also gets a cutoff frequency of 13 GHz at a gate voltage of 5.5 V.     

1200V大容量SiC MOSFET器件研制

采用平面栅MOSFET器件结构,结合优化终端场限环设计、栅极bus-bar设计、JFET注入设计以及栅氧工艺技术,基于自主碳化硅工艺加工平台,研制了1200V大容量SiC MOSFET器件.测试结果表明,器件栅极击穿电压大于55V,并且实现了较低的栅氧界面态密度.室温下,器件阈值电压为2.7V,单芯片电流输出能力达到50A,器件最大击穿电压达到1600V.在175℃下,器件阈值电压漂移量小于0.8V;栅极偏置20V下,泄漏电流小于45nA.研制器件显示出优良的电学特性,具备高温大电流SiC芯片领域的应用潜力.     

A submicrometer lifted diffused-layer MOSFET

A new lifted diffused-layer (LID) MOSFET has been devised and fabricated, where the major portions of the source/drain (S/ D) diffused layers are placed on top of the field insulator to reduce S/D parasitic capacitances. The primary feature of this MOSFET is that the structure and processing are especially developed for submicrometer gate lengths. The fabricated LID MOSFET with a 0.5-µm gate length and a 10-nm gate oxide thickness showed good electrical characteristics, such as a maximum transconductance of 115 mS/mm and an inverter delay time of 59 ps/stage.     

Raised source/drain MOSFET with dual sidewall spacers

A raised source/drain (S/D) MOSFET with sidewall spacers formed both before and after selective epitaxial silicon deposition in S/D regions is discussed. The second spacer overlies any faceted regions of the epitaxial silicon near the gate edge and has advantages for MOSFETs with implant-doped or in-situ doped epitaxial silicon regions. In particular, the spacer can prevent S/D dopants from being implanted through any thinner faceted regions near the gate edge, which would otherwise result in a deeper than desired junction depth in the silicon substrate. Additionally, the spacer can prevent source-to-substrate salicide shorts through the thinner faceted regions     

A new grounded lamination gate (GLG) for diminished fringe-capacitance effects in high-/spl kappa/ gate-dielectric MOSFETs

A grounded lamination gate (GLG) structure for high-/spl kappa/ gate-dielectric MOSFETs is proposed, with grounded metal plates in the spacer oxide region. Two-dimensional device simulations performed on the new structure demonstrate a significant improvement with respect to the threshold voltage roll-off with increasing gate-dielectric constant (due to parasitic internal fringe capacitance), keeping the equivalent oxide thickness same. A simple fabrication procedure for the GLG MOSFET is also presented.     

A GaAs 1-kbit static RAM with a shallow recessed-gate structure FET

A novel GaAs FET structure, the shallow recessed-gate structure, has been proposed and applied to a 1-kbit static RAM. In order to decrease the source resistance Rsand gate capacitance Cg, the shallow n⁺implanted layer was formed between the gate and source/drain region; then the gate region was slightly recessed. This FET has a high transconductance gm, low source resistance Rs, small gate capacitance Cg, and small deviation of threshold voltagepart V_{th}, and thus is suitable for high-speed GaAs LSI's. A 1-kbit static RAM has been designed and fabricated applying this FET structure and an access time of 3.8 ns with 38- mW power dissipation has been obtained.     

Drastic reduction of gate leakage in InAlAs/InGaAs HEMT's using apseudomorphic InAlAs hole barrier layer

Impact ionization in the channel of InAlAs/InGaAs HEMT's was shown to be a reason for excess gate leakage current. Hot electrons in the high field region of the channel under the gate generate electron-hole pairs. The generated holes can reach the gate (gate leakage) as well as the source, the electrons flow to the drain (kink effect). The number of holes reaching the gate strongly depends on the valence band discontinuity. In order to increase this valence band discontinuity a thin pseudomorphic InAlAs layer with high Al-content was inserted in the spacer of an InAlAs/InGaAs HEMT. The efficiency of this hole barrier was measured by photocurrent and DC measurements, while its influence on transport characteristics was measured by Hall and RF measurements. A reduction of gate leakage by a factor of 200 is demonstrated     

Ultrathin-body SOI MOSFET for deep-sub-tenth micron era

A 40-nm-gate-length ultrathin-body (UTB) nMOSFET is presented with 20-nm body thickness and 2.4-nm gate oxide. The UTB structure eliminates leakage paths and is an extension of a conventional SOI MOSFET for deep-sub-tenth micron CMOS. Simulation shows that the UTB SOI MOSFET can be scaled down to 18-nm gate length with <5 nm UTB. A raised poly-Si S/D process is employed to reduce the parasitic series resistance     

GaAs MOSFET with oxide gate dielectric grown by atomic layer deposition

For the first time, a III-V compound semiconductor MOSFET with the gate dielectric grown by atomic layer deposition (ALD) is demonstrated. The novel application of the ALD process on III-V compound semiconductors affords tremendous functionality and opportunity by enabling the formation of high-quality gate oxides and passivation layers on III-V compound semiconductor devices. A 0.65-/spl mu/m gate-length depletion-mode n-channel GaAs MOSFET with an Al/sub 2/O/sub 3/ gate oxide thickness of 160 /spl Aring/ shows a gate leakage current density less than 10/sup -4/ A/cm/sup 2/ and a maximum transconductance of 130 mS/mm, with negligible drain current drift and hysteresis. A short-circuit current-gain cut-off frequency f/sub T/ of 14.0 GHz and a maximum oscillation frequency f/sub max/ of 25.2 GHz have been achieved from a 0.65-/spl mu/m gate-length device.     

A new method utilizing Ti—silicide oxidation for the fabrication of a MOSFET with a self-aligned Schottky source/drain

A short and simple fabrication process to realize a MOSFET with a self-aligned Schottky source/drain is described. This process utilizes Ti-silicide deposition and its oxidation, which simultaneously leads to the self-aligning formation of silicided source/drain regions isolated from gate electrodes and the formation of intermediate insulator between Al wire and gate level. The isolation between source/drain and gate has been realized by oxidation at 800°C for 180 min. Sheet resistance of about 4 Ω on the source/drain level has been achieved. This MOSFET has also minimized the "short-channel effect."     

A new symmetrical double gate nanoscale MOSFET with asymmetrical side gates for electrically induced source/drain

In this paper, we present the unique features exhibited by a novel double gate MOSFET in which the front gate consists of two side gates as an extension of the source/drain. The asymmetrical side gates are used to induce extremely shallow source/drain regions on either side of the main gate. Using two-dimensional and two-carrier device simulation, we have investigated the improvement in device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing and the hot carrier effect. Based on our simulation results, we demonstrate that the proposed symmetrical double gate SOI MOSFET with asymmetrical side gates for the induced source/drain is far superior in terms of controlling the short-channel effects when compared to the conventional symmetrical double gate SOI MOSFET. We show that when the side gate length is equal to the main gate length, the device can be operated in an optimal condition in terms of threshold voltage roll-off and hot carrier effect. We further show that in the proposed structure the threshold voltage of the device is nearly independent of the side gate bias variation.