A programmable gain amplifier with a DC offset calibration loop for a direct-conversion WLAN transceiver

A high-linearity PGA (Programmable Gain Amplifier) with DC offset calibration loop is proposed in this paper. The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity. A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem. This PGA is fabricated in TSMC 0.13um CMOS technology. The measurements show that the receiver PGA （RXPGA）provides 64dB gain range with a step of 1dB, and the transmitter PGA（TXPGA） covers 16dB gain. The RXPGA consumes 18mA and the TXPGA consumes 7mA (I and Q path) under 3.3V supply. The bandwidth of the multi-stage PGA is higher than 20MHz. In addition, the DCOC (DC offset cancellation) circuit shows 10KHz of HPCF (high pass cutoff frequency) and the DCOC settling time is less than 0.45µs.     

一种应用于直接变频WLAN接收机带数字辅助直流失调消除功能的可变增益放大器

本文提出了一种包含数字辅助直流失调消除(DCOC)功能,应用于直接变频无线局域网接收机的可变增益放大器(PGA)电路。该PGA采用0.13微米标准CMOS工艺实现,芯片面积0.39平方毫米,在1.2伏电源电压下的功耗为6.5毫瓦。通过采用单环路单数模转换器(DAC)混合信号直流失调消除结构,直流失调消除的最小建立时间减小至1.6微秒,同时可变增益放大器的增益能够在-8分贝到54分贝间以2分贝的步长变化。该直流失调消除环路采用了一种分段式数模转换器以在不牺牲精度的前提下降低设计复杂度,并采用了特定的数字控制算法使得环路的直流失调消除响应时间能够在快慢两种模式间动态切换,以使可变增益放大器符合无线局域网应用的要求。     

A direct-conversion WLAN transceiver baseband with DC offset compensation and carrier leakage reduction

A dual-band direct-conversion WLAN transceiver baseband compliant with the IEEE 802.11 a/b/g standards is described.Several critical techniques for receiver DC offset compensation and transmitter carrier leakage rejection calibration are presented that enable the direct-conversion architecture to meet all WLAN specifications.The receiver baseband VGA provides 62 dB gain range with steps of 2 dB and a DC offset cancellation circuit is introduced to remove the offset from layout and self-mixing.The calibra...     

一种带有直流失调和载波泄漏矫正系统的直接变频WLAN收发机基带电路

本文介绍了一种基于IEEE 802.11a/b/g标准的双频段直接变频WLAN收发机基带电路,并引入了一些用于消除接收机直流失调和发射机载波泄漏的关键技术,从而使得该直接变频结构满足WLAN的性能指标。在接收机基带中,可变增益放大器提供62dB的增益范围且步长为2dB;直流失调矫正电路用来消除由版图不匹配和自混频造成的误差。该矫正环路有着不随增益调节而变化的高通极点和较快的稳定时间,后者通过在接收前导序列时设定1MHz的高通极点而在正常接收数据时设定30KHz的极点得以实现。发射机基带采用基于片上AD和DA的自动矫正系统来抑制载波泄漏,AD在矫正完成之后会自动关闭从而可以节省功耗。此电路采用0.35微米锗硅工艺并工作在2.85V电源电压下,接收基带放大器和直流失调消除电路共消耗17.52mA,而发射载波泄漏矫正环路共消耗8.3mA（矫正完成后为5.88mA）;其相应的芯片面积分别为0.68mm2和0.18mm2。     

CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

A low-power high-linearity linear-in-dB variable gain amplifier (VGA) with novel DC offset calibration loop for direct-conversion receiver (DCR) is proposed in this paper. The proposed VGA uses the differential-ramp based technique, digitally programmable gain amplifier (PGA) can be converted to analog controlled dB-linear VGA. An operational amplifier (OPAMP) utilizing an improved Miller compensation approach is adopted in this VGA design. The proposed VGA shows a 57dB linear range. The DC offset cancellation (DCOC) loop is based on a continuous time feedback that includes Miller effect and linear rang operation MOS transistor to realize large value capacitor and resistor to solve the DC offset problem, respectively. The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement. Fabricated in SMIC 0.13 m CMOS technology, this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58mm2 of chip area including bondpads. In addition, the DCOC circuit shows 500Hz high pass cutoff frequency (HPCF) and the measured residual DC offset at the output of VGA is less than 2 mV.     

CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

A low-power high-linearity linear-in-dB variable gain amplifier(VGA) with novel DC offset calibration loop for direct-conversion receiver(DCR) is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier(PGA) can be converted to an analog controlled dB-linear VGA. An operational amplifier(OPAMP) utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation(DCOC) loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm~2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency(HPCF) and the measured residual DC offset at the output of VGA is less than 2 mV.     

一种应用于高清视频模拟前端的多功能开关电容可编程增益放大器

A multifunctional programmable gain amplifier(PGA) that provides gain and offset adjusting abilities for high-definition video analog front-ends(AFE) is presented. With a switched-capacitor structure, the PGA also acts as a sample and holder of the analog-to-digital converter(ADC) in the AFE to reduce the power consumption and chip area of the whole AFE. Furthermore, the PGA converts the single-ended video signal into differential signal for the following ADC to reject common-mode noise and interferences. The 9-bit digital-to-analog converter(DAC) for gain and offset adjusting is embedded into the switched capacitor networks of the PGA. A video AFE integrated circuit based on the proposed PGA is fabricated in a 0.18- m process. Simulation and measurement results show that the PGA achieves a gain control range of 0.90 to 2.34 and an offset control range of –220 to220 mV while consuming 10.1 mA from a 1.8 V power supply.     

一种无线宽带收发机载波泄漏校准和补偿技术

A carrier leakage calibration and compensation technique based on digital baseband for a wideband wireless communication transceiver is proposed. The digital baseband transmits a calibration signal, samples the signal which passes through the transmitter path and the calibration loop in the RF chip, measures the carrier leakage by analyzing the sampled data and compensates it. Compared with a self-calibration technique in the RF chip, the proposed technique saves area and power consumption for the wireless local area network （WLAN） solution. This technique has been successfully used for 802.1 In system and satisfies the requirement of the standard by achieving over 50 dB carrier leakage suppression.     

64dB二进制增益控制带有DCOC和AB类buffer的可编程增益放大器

本文设计了一款二进制增益控制,带有直流失调消除（DCOC）电路以及AB类输出buffer的可编程增益放大器。该放大器采用二极管连接负载的差分放大器结构,电路性能对温度变化及工艺偏差不敏感。根据测试,通过6位数字信号控制,电路可以实现-2dB ~ 61dB的增益动态范围,增益步长1dB,步长误差在 0.38dB以内,最小3dB带宽为92MHz,在低增益模式下,IIP3可达17dBm,1dB压缩点可达5.7dBm。DCOC电路可使该放大器应用于直接变频接收机中,而AB类输出buffer则降低了电路的静态功耗。     

程控增益低噪声宽带直流放大器的设计

介绍了程控增益低噪声宽带直流放大器的设计原理及流程。采用低噪声增益可程控集成运算放大器AD603和高频三极管2N2219和2N2905等器件设计了程控增益低噪声宽带直流放大器,实现了输入电压有效值小于10mV,输出信号有效值最大可达10V,通频带为0～8MHz,增益可在0～50dB之间5dB的步进进行控制,最高增益达到53dB,且宽带内增益起伏远小于1dB的两级宽带直流低噪声放大器的设计。     

一种应用于直接变频系统的低功耗混合信号直流失调消除电路

A low power mixed signal DC offset calibration (DCOC) circuit for direct conversion receiver applications is designed. The proposed DCOC circuit features low power consumption, fast settling time and a small die area by avoiding the trade-off between loop response time and the high pass frequency of the DCOC servo loop in conventional analog DCOC systems. By applying the proposed DC offset correction circuitry, the output residue DC offset voltages are reduced to less than 38 mV and the DCOC loop settling time is less than 100 μs. The DCOC chip is fabricated in a standard 0.13-μm CMOS technology and drains only 196 μA from a 1.2-V power supply with its chip area of only 0.372 × 0.419 mm².     

一种带新型直流失调补偿电路的模拟数字控制可配置的自动增益控制器

本文提出一种可用于零中频接收机的模拟/数字控制可配置的自动增益控制环路的设计,应用一种新型的直流失调消除电路。这种自动增益控制环路可配置于模拟或者数字控制,以便与不同的基带芯片兼容。本文更进一步提出了一种新型的直流失调消除电路,这种直流失调消除电路实现了低于10KHz的下限截止频率（HPCF,high pass cutoff frequency）。自动增益控制环路电路采用0.18um CMOS工艺。当配置于模拟控制模式下,这种自动增益控制环路的增益动态范围为70dB,3dB带宽大于60M。当配置于数字控制模式下,通过5比特的数字控制码控制,这种自动增益控制环路的增益动态范围为64dB,步进精度2dB,步进误差小于0.3dB。当输入引入40mV直流失调,电路输出直流失调电压小于1.5mV。电路整体功耗小于3.5mA,面积800um*300um。     

A low power mixed signal DC offset calibration circuit for direct conversion receiver applications

A low power mixed signal DC offset calibration(DCOC) circuit for direct conversion receiver applications is designed.The proposed DCOC circuit features low power consumption,fast settling time and a small die area by avoiding the trade-off between loop response time and the high pass frequency of the DCOC servo loop in conventional analog DCOC systems.By applying the proposed DC offset correction circuitry,the output residue DC offset voltages are reduced to less than 38 mV and the DCOC loop settling time is less than 100μs.The DCOC chip is fabricated in a standard 0.13-μm CMOS technology and drains only 196μA from a 1.2-V power supply with its chip area of only 0.372×0.419 mm~2.     

A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit

An analog/digital reconfigurable automatic gain control(AGC) circuit with a novel DC offset cancellation circuit for a direct-conversion receiver is presented.The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips.What’s more,a novel DC offset cancellation(DCOC) circuit with an HPCF(high pass cutoff frequency) less than 10 kHz is proposed.The AGC is fabricated by a 0.18μm CMOS process.Under analog control mode,the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz.Under digital control mode,through a 5-bit digital control word,the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB.The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV,while the offset voltage of 40 mV is introduced into the input.The overall power consumption is less than 3.5 mA,and the die area is 800×300μm~2.     

基于斩波技术的CMOS运算放大器失调电压的消除设计

实现传感器系统的高分辨率,要求其内部运算放大器具有低失调电压和低噪声的性能,为此介绍了一种可减少运算放大器的失调电压和低频噪声的斩波技术,并基于该技术进行温度传感器中CMOS运算放大电路失调电压的消除设计,最后通过SPICE仿真分析来权衡电路各参数的设定。     

一种带宽为3.8GHz，增益步长为0.1dB的可编程增益放大器

A broadband programmable gain amplifier（PGA） with a small gain step and low gain error has been designed in 0.13 m CMOS technology. The PGA was implemented with open-loop architecture to provide wide bandwidth. A two-stage gain control method, which consists of a resistor ladder attenuator and an active fine gain control stage, provides the small gain step. A look-up table based gain control method is introduced in the fine gain control stage to lower the gain error.The proposedPGAshows a decibel-linear variable gainfrom4 to20 dB with a gain step of 0.1 dB and a gain error less than˙0.05 dB. The 3-dB bandwidth and maximum IIP3 are 3.8 GHz and 17 dBm, respectively.     

A high-resolution multi-phase delay-locked loop with offset locking technique

In this work, we propose a new type of high-resolution delay-locked loop (DLL) which achieves the performance of high-resolution output by offset locking techniques without restrictions of intrinsic delay in the delay cell. Compared to traditional multi-phase clock generator, this architecture has the features of small size, low jitters, low-power consumption and high resolution. This DLL has been fabricated in 0.35 μm complementary metal-oxide-semiconductor (CMOS) process. The measured root-mean-square and peak-to-peak jitters are 2.89 ps and 31.1 ps at 250 MHz, respectively. The power dissipation is 68 mW for a supply voltage of 3.3 V. The maximum resolution of this work is 144 p and the intrinsic delay of 0.35 μm CMOS process is 220 ps. Comparing with intrinsic delay, the improvement of maximum resolution is 34.5%.     

A continuously and widely tunable analog baseband chain with digital-assisted calibration for multi-standard DBS applications

This paper presents a continuously and widely tunable analog baseband chain with a digital-assisted calibration scheme implemented on a 0.13μm CMOS technology.The analog baseband is compliant with several digital broadcasting system（DBS） standards,including DVB-S,DVB-S2,and ABS-S.The cut-off frequency of the baseband circuit can be changed continuously from 4.5 to 32 MHz.The gain adjustment range is from 6 to 55.5 dB with 0.5 dB step.The calibration includes automatic frequency tuning（AFT） and automatic DC offset calibration （DCOC） to achieve less than 6%cut-off frequency deviation and 3 mV residual output offset.The out-of-band IIP2 and IIP3 of the overall chain are 45 dBm and 18 dBm respectively,while the input referred noise（IRN） is 17.4 nV/Hz^1/2.All circuit blocks are operated at 2.8 V from LDO and consume current of 20.4 mA in the receiving mode.