Analysis and application of new quasi-network characteristics of nonuniform mesh in FDTD simulation

The equation of computing the reflection coefficient between two meshes of different sizes is derived. Using the equation, quasi-network characteristics of nonuniform mesh for the finite-difference time-domain technique is found and analyzed. The so-called mesh network (MN) here is a kind of structure composed of the sections of mesh in cascade. The cell sizes of these sections change regularly. By means of choosing the number of mesh sections, length of each section, and cell sizes, some novel network characteristics are obtained, which can be used to match the reflecting wave of nonuniform mesh or improve the transmitted characteristics for a mesh wave to travel along the nonuniform mesh. Formulas for analyzing the MN are given. The characteristics are realized in both one- and three-dimensional cases. The applications and advantages of the MN are shown by computing three different structures, i.e., microstrip-gap capacitor, parallel-coupling filter, and microstrip slot-line transformer.     

非均匀传输线综合的特征法

本文利用特征法对无耗非均匀传输线进行了综合。在二倍于传输线延时的时间范围内给定时域反射电压响应的ｍ个取样值，则非均匀传输线可由ｍ段长度不等、延时为相应时间取样间隔的均匀线近似，各均匀传输线段的特性阻抗唯一求出。     

Hardware efficient fast parallel FIR filter structures based on iterated short convolution

This paper presents an iterated short convolution (ISC) algorithm, based on the mixed radix algorithm and fast convolution algorithm. This ISC-based linear convolution structure is transposed to obtain a new hardware efficient fast parallel finite-impulse response (FIR) filter structure, which saves a large amount of hardware cost, especially when the length of the FIR filter is large. For example, for a 576-tap filter, the proposed structure saves 17% to 42% of the multiplications, 17% to 44% of the delay elements, and 3% to 27% of the additions, of those of prior fast parallel structures, when the level of parallelism varies from 6 to 72. Their regular structures also facilitate automatic hardware implementation of parallel FIR filters.     

On simplified order-one factorizations of paraunitary filterbanks

This paper revisits the order-one factorization of causal finite impulse response (FIR) paraunitary filterbanks (PU FBs). The basic form of the factorization was proposed by Vaidyanathan et al. in 1987, which is a cascade of general unitary matrices separated by diagonal delay matrices with arbitrary number of delay elements. Recently, Gao et al. have proved the completeness of this factorization and developed a more efficient structure that only uses approximately half number of free parameters. In this paper, by briefly analyzing Gao et al.'s derivation, we first point out that Gao et al.'s factorization contains redundant free parameters. Two simplified structures of Vaidyanathan's factorization are then developed, i.e., a post-filtering-based structure and a prefiltering-based structure. Our simplification relies on consecutive removal of extra degrees of freedom in adjacent stages, which is accomplished through the C-S decomposition of a general unitary matrix. Since the conventional C-S decomposition leads to a redundant representation, a new C-S decomposition is developed to minimize the number of free parameters by further incorporating the Givens rotation factorization. The proposed structures can maintain the completeness and the minimality of the original lattice. Compared with Gao et al.'s factorization, our derivations are much simpler, while the resulting structures contain fewer free parameters and less implementation cost. Besides, these new factorizations indicate that for a PU FB with a given filter length, the symmetric-delay factorization offers the largest degrees of design freedom. Several design examples are presented to confirm the validity of the theory.     

一种基于迭代短卷积算法的低复杂度并行FIR滤波器结构

该文基于快速卷积算法,提出一种适用于线性相位FIR滤波器的并行结构。该结构采用快速卷积算法减少子滤波器个数,同时让尽可能多的子滤波器具有对称系数,然后利用系数对称的特性减少子滤波器模块中的乘法器数量。对于具有对称系数的FIR滤波器,提出的并行结构能够比已有的并行FIR结构节省大量的硬件资源,尤其当滤波器的抽头数较大时效果更明显。具体地,对一个4并行144抽头的FIR滤波器,提出的结构比改进的快速FIR算法(Fast FIR Algorithm, FFA)结构节省36个乘法器(14.3%),23个加法器(6.6%)和35个延时单元(11.0%)。     

A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic

In this paper, we have analyzed the register complexity of direct-form and transpose-form structures of FIR filter and explored the possibility of register reuse. We find that direct-form structure involves significantly less registers than the transpose-form structure, and it allows register reuse in parallel implementation. We analyze further the LUT consumption and other resources of DA-based parallel FIR filter structures, and find that the input delay unit, coefficient storage unit and partial product generation unit are also shared besides LUT words when multiple filter outputs are computed in parallel. Based on these finding, we propose a design approach, and used that to derive a DA-based architecture for reconfigurable block-based FIR filter, which is scalable for larger block-sizes and higher filter-lengths. Interestingly, the number of registers of the proposed structure does not increase proportionately with the block-size. This is a major advantage for area-delay and energy efficient high-throughput implementation of reconfigurable FIR filters of higher block-sizes. Theoretical comparison shows that the proposed structure for block-size 8 and filter-length 64 involves 60% more flip-flops, 6.2 times more adders, 3.5 times more AND-OR gates, and offers 8 times higher throughput. ASIC synthesis result shows that the proposed structure for block-size 8 and filter-length 64 involves 1.8 times less area-delay product (ADP) and energy per sample (EPS) than the existing design, and it can support 8 times higher throughput. The proposed structure for block sizes 4 and 8, respectively, consumes 38% and 50% less power than the exiting structure for the same throughput rates on average for different supply voltages.     

Nonuniform filter banks: a reconstruction and design theory

A general procedure for the design of analysis-synthesis systems based on nonuniform filter banks is described. The procedure is based on a time-domain analysis of nonuniform systems, which results in a set of conditions for the exact reconstruction of the input signal at the output. These conditions are used as part of a powerful iterative algorithm for designing finite impulse response (FIR) filter banks with an arbitrary nonuniform frequency resolution. This new framework permits the design of systems with arbitrary rational decimation rates in different bands. Systems based on maximally or nonmaximally decimated filter banks, on low and minimum delay systems, and on block decimators are also among the systems that can be designed using this method     

Realization of 2-D Variable IIR Digital Filter Structures with a Small Amount of Calculations for Coefficient Update

This paper proposes 2-D variable IIR digital filter structures with a small amount of calculations for coefficient update. The proposed realization method uses the 2-D parallel allpass structure derived from the separable denominator 2-D filter as the prototype structure for 2-D variable digital filters. In order to reduce the amount of calculations, all the redundant first-order complex allpass sections are combined by modularization of the variable structure. Furthermore, we can realize a very compact variable structure with a minimal number of first-order complex allpass sections by combining complex allpass sections with their complex conjugate allpass sections. Comparison of the calculation loads of the variable structures is presented to demonstrate that the amount of calculations for coefficient update of the proposed variable structure is far less than that of the original and the modular variable structure.     

M-Channel Nonlinear Phase Filter Banks in Image Compression: Structure, Design, and Signal Extension

This paper describes a transform coding technique based on M-channel perfect reconstruction filter banks with a nonlinear phase. In contrast with linear-phase filter banks, the nonlinearity provides an extra degree of freedom that can be used to design a more efficient transform. We present new lattice structures of paraunitary and perfect reconstruction (biorthogonal) filter banks, which can be implemented with a lower computational complexity and/or represented by a few free parameters, through the decomposition of the lattice blocks and the displacement across the delay block. We further discuss a smooth extension method for nonlinear-phase filter banks to obtain a nonexpansive transform. The promise of our proposed approaches is demonstrated through several design examples, extended signals and compression results     

Polyphase FIR Networks Based on Frequency Sampling for Multirate DSP Applications

It is well known that the frequency sampling approach to the design of Finite Impulse Response digital filters allows recursive implementations which are computationally efficient when most of the frequency samples are integers, powers of 2 or null. The design and implementation of decimation (or interpolation) filters using this approach is studied herein. Firstly, a procedure is described which optimizes the tradeoff between the stopband energy and the deviation of the passband from the ideal filter. The search space is limited to a small number of samples (in the transition band), imposing the condition that the resulting filter have a large number of zeros in the stopband. Secondly, three different structures to implement the decimation (or interpolation) filter are proposed. The implementation complexity, i.e., the number of multiplications and additions per input sample, are derived for each structure. The results show that, without taking into account finite word-length effects, the most efficient implementation depends on the filter length to decimation (or interpolation) ratio.     

Coupled inductor, constant resistance, broadband delay filter

This paper develops a three-terminal delay filter whose topology is an interconnection of only ideally lossless, coupled inductors and capacitors. In the absence of significant capacitive loading at the input and/or output ports, the proposed filter emulates an allpass network whose low frequency delay is twice that afforded by the poles of the proposed circuit. Moreover, the driving point input and output impedances of the structure are frequency invariant resistances whose values over the frequency spectra of interest are independent of the envelope delays achieved. These impedance characteristics allow for the convenient implementation of a cascade of match-terminated delay filter sections, thereby allowing for reasonably large envelope delays without incurring bandwidth penalties in either the magnitude or the delay responses. An example demonstrates the feasibility of designing a filter providing zero frequency delays in the mid-hundreds of picoseconds that remain nominally constant for signal frequencies extending through a few gigahertz. Correspondingly, the magnitude responses of these delay structures offer 3-dB bandwidths that can be significantly larger than the frequencies at which the observed envelope delays decay monotonically to a user-defined percentage of their respective zero frequency values.     

Parallel processing architectures for rank order and stack filters

Many architectures have been proposed for rank order and stack filtering. To achieve additional speedup in these structures requires the use of parallel processing techniques such as pipelining and block processing. Pipelining is well understood but few block architectures have been developed for rank order and stack filtering. Block processing is essential for additional speedup when the original architecture has reached the throughput limits caused by the underlying technology. A trivial block structure simply repeats a single input, single output structure to generate a multiple input, multiple output structure. Therefore the architecture can achieve speedups equal to the number of multiple outputs or the block size. However, unlike linear filters, the rank order and stack filter outputs are calculated using comparisons. It is possible to share these comparisons within the block structure and thus substantially reduce the size of the block structure. The authors introduce a systematic method for applying block processing to rank order filters and stack filters. This method takes advantage of shared comparisons within the block structure to generate a block filter with shared substructures whose complexity is reduced by up to one-third compared to the original filter structure times the block size. Furthermore, block processing is important for the generation of low power designs. A block structure can trade its increased speedup for a throughput equal to the original single output architecture but with a significantly lower power requirement. The power reduction in the trivial block structures is limited by the power supply voltage. They demonstrate how block structures with shared substructures allow them to continue decreasing the power consumption beyond the limit imposed by the supply voltage     

Low- Cost Parallel FIR Filter Structures With 2-Stage Parallelism

Based on recently published low-complexity parallel finite-impulse response (FIR) filter structures, this paper proposes a new parallel FIR Filter structure with less hardware complexity. The subfilters in the previous parallel FIR structures are replaced by a second stage parallel FIR filter. The proposed 2-stage parallel FIR filter structures can efficiently reduce the number of required multiplications and additions at the expense of delay elements. For a 32-parallel 1152-tap FIR filter, the proposed structure can save 5184 multiplications (67%), 2612 additions (30%), compared to previous parallel FIR structures, at the expense of 10089 delay elements (-133%). The proposed structures will lead to significant hardware savings because the hardware cost of a delay element is only a small portion of that of a multiplier, not including the savings in the number of additions     

宽带波束形成中小数时延滤波器设计

以电子战中的宽带波束形成器设计为背景,阐述了数字延迟线与小数时延滤波器相结合的时域波束形成方案,并引入广泛应用于多速率系统中的Farrow结构可变时延滤波器。针对宽带Farrow结构滤波器中乘法器资源消耗量较大的问题,采用对称结构的子滤波器系数求解方法,最后通过多次仿真验证了设计的合理性并给出相关设计参数的一般取值,为后续工程上的实现奠定了理论基础。     

A Very Efficient Storage Structure for DWT and IDWT Filters

In this paper, we present an area-efficient storage and routing structure to be used as part of either a DWT or an IDWT filter. Such efficient structures are necessary for the single chip implementation of multidimensional DWT and IDWT filters for processing images and video. While the storage structures described in previously published architectures were adequate for the 1D DWT/IDWT filter, they do not scale well to a multidimensional implementation. The storage structure design and implementation described in this paper utilizes a combination of well-known efficient RAM cells with simple control to achieve compact size and scalability. When compared to other alternatives, the structure uses less power.In this paper, we examine the problem of constructing, on a single chip, filters for both the multidimensional Discrete Wavelet Transform (DWT) and the multidimensional Inverse Discrete Wavelet Transform (IDWT). We will use the following example to illustrate where the difficulty lies in constructing such a chip. Consider a filter that executes transforms on 2D images at the rate of 30 images per second. Furthermore, the size N × N of the images is 1024 × 1024, the length L of the filter is 8, the number of octaves O to be generated is 4, and the arithmetic precision P is 24. In image compression, such a filter would be a good candidate for the replacement of the filters presently used to perform the block Discrete Cosine Transform (DCT).     

High-speed digital filtering: Structures and finite wordlength effects

This paper is a study of high-throughput filter structures such as block structures and their behavior in finite precision environments. Block structures achieve high throughput rates by using a large number of processors working in parallel. It has been believed that block structures which are relatively robust to round-off noise must also be robust to coefficient quantization errors. However, our research has shown that block structures, in fact, have high coefficient sensitivity. A potential problem that arises as a result of coefficient quantization is a periodically time-varying behavior exhibited by the realized filter. We will demonstrate how finite wordlength errors can change a nominally time-invariant filter into a time-varying system. We will identify the block structures that have low coefficient sensitivity, and develop high-speed structures that are immune to the time-varying problems caused by coefficient quantization.     

Linear-phase perfect reconstruction filter bank: lattice structure,design, and application in image coding

A lattice structure for an M-channel linear-phase perfect reconstruction filter bank (LPPRFB) based on the singular value decomposition (SVD) is introduced. The lattice can be proven to use a minimal number of delay elements and to completely span a large class of LPPRFBs: all analysis and synthesis filters have the same FIR length, sharing the same center of symmetry. The lattice also structurally enforces both linear-phase and perfect reconstruction properties, is capable of providing fast and efficient implementation, and avoids the costly matrix inversion problem in the optimization process. From a block transform perspective, the new lattice can be viewed as representing a family of generalized lapped biorthogonal transform (GLBT) with an arbitrary number of channels M and arbitrarily large overlap. The relaxation of the orthogonal constraint allows the GLBT to have significantly different analysis and synthesis basis functions, which can then be tailored appropriately to fit a particular application. Several design examples are presented along with a high-performance GLBT-based progressive image coder to demonstrate the potential of the new transforms     

On the design and realization of a class of uniform single rate FIR DFT filter banks

In this paper we present a computationally efficient realization of single rate uniform FIR filter banks for audio and spectral analysis applications. The channel filters in the analysis bank are represented as modulated versions of a prototype narrowband lowpass FIR filter. Using the IFIR filter design technique [23], [24], this prototype lowpass filter can be designed very efficiently as a cascade of two subfilters. The IFIR filter design is extended for the two-branch realization of uniform filter banks with overlapping channels. A generalized structure is presented which can be used for bothodd andeven stacking arrangements of the channels. The shaping filter structures for the two branches are realized from a single delay line and a single set of filter coefficients, thus conserving the total number of multipliers and delays in the overall realization. The postfilter structure, in conjunction with the Generalized DFT matrices, performs the channel selection. The Generalized DFT matrices are used to provide the necessary modulation for the postfilter coefficients so that the appropriate passbands are selected for each channel of the analysis bank. This leads to a polyphase network realization of the postfilter structure. We derive conditions so that the original input signal can be exactly reconstructed from the channel signals.This work was supported in part by the National Science Foundation under Grant MIP 85-08017 and in part by a University of California MICRO Grant with matching support from the Rockwell Corporation and the Intel Corporation.     

Focusing filters for wide-band direction finding

A time-domain equivalent of the coherent signal-subspace transformations (CST) is established for wideband direction finding in a possible multipath environment using general arrays. Time-domain equivalents of focusing are derived based on the least squared error approach for general transformations, and the Taylor series expansion approach for closed-form transformations. The preprocessor is realized by a multichannel digital finite impulse response filter. For diagonal transformations, the problem reduces to implementing different delays at each sensor, which in turn leads to computational simplicity. Various tapped delay line filters for realizing an arbitrary delay are proposed and compared. Simulation results reveal that low-order filter structures in the time domain achieve similar performance to the frequency domain approach, even at detection and resolution thresholds     

一种Farrow结构数字延时滤波器的设计

普通数字延时滤波器虽然结构简单,但系数计算过程复杂,在延时参数快速变化时,系数更新速度无法满足实时性要求,在工程应用上受限制。采用Farrow结构数字延时滤波器能够更加灵活高效地进行分数延时滤波,延时参数改变时,无需重新计算滤波器系数,更容易在现场可编程门阵列(FPGA)上实现。介绍了一种Farrow结构数字延时滤波器,提出采用基于对称结构的滤波器系数求解方法,并经过加权优化,获得最终Farrow滤波器的系数。系数计算过程中,通过对设计所得Farrow滤波器延时精度和误差的分析,调整加权因子的取值和滤波器阶数,进而提高延时精度。计算机仿真结果证明了加权对称系数求解Farrow滤波器系数方法的有效性和实用性。