一种设计同步时序逻辑电路的新方法

提出了一种设计同步时序逻辑电路的新方法。根据触发器 (FF)基本特性 ,可从电路的状态转换图上直接求得触发器置位、复位函数 ,进而确定触发器的激励方程。具体设计实例表明该方法简捷、高效 ,设计电路功能正确     

一种同步和异步时序电路统一分析的新方法

本文引入触发器的跳变函数，讨论触发器的时钟激励方程，从而提出一种同步和异步时序电路统一分析新方法。该方法的有效性和可操作性已由实例予以证明。     

一种基于状态转换图的时序电路等价验证算法

提出一种基于状态转换图的时序电路等价验证算法。此算法通过验证两时序电路的状态转换图是否同构．得到两电路是否等价的信息。若两状态转换图同构，则两图中的状态可一一匹配为等价状态对，算法将状态转换图存储为待验证等价状态对的形式，若所有待验证等价状态对均为等价，则两时序电路等价，反之，则不等价。此算法对ISCAS89测试电路进行验证，与基于BDD方法的SIS系统和基于时间帧展开算法相比，均有较好的结果。     

边沿取样电路和同步动态时序电路综合

本文提出用电容代替触发器作为记忆元件的双边沿同步动态时序电路（ＳＤＳＣ）的综合方法。基于电路三要素（信号、网络和负载）理论,首先推导出边沿取样定理;接着研究普适双边沿状态图和电路图的关系,再将卡诺图方法由门级发展到元件级;最后提出ＳＤＳＣ的状态编码原则,从而形成有效的ＳＤＳＣ的综合方法,用此方法设计了一些结构极简单的动态电路,诸如错码检测电路仅用２２个ＭＯＳ管,８４２１ＢＣＤ码二进制计数器仅用３１     

时序电路的状态验证研究与设计

采用二元判定图（ＢＤＤ）作为工具来描述时序电路是非常有意义和有效的，本文通过对ＢＤＤ的简化达到对状态变换图（ＳＴＧ）输入，路径和状态的压缩，从而提高状态遍历的效率，另外根据电路的特点，提出状态冲突和不相交分解的启发技术以有效地完成验证。     

基于蚂蚁算法和遗传算法的同步时序电路初始化

本文针对时序电路的初始化提出一种新的实现方法．在电路没有设置一个总复位信号的情况下，必须。使得电路状态由未知变为已知，电路才能正常工作．本文用逻辑初始化方式，通过将蚂蚁算法和遗传算法交叉生成初始化序列，最大限度地初始化触发器，实现电路的初始化．实验结果表明，这种方法和其他同类算法相比较能在初始化触发器数量和序列长度上取得很好的结果．     

一种新的ASM设计法

本文提出了用纯二值结构的三值触发器作为基本存贮单元的ASM one-zero-hot设计法。     

交叉耦合绝热动态触发器及同步动态时序电路

本文提出交叉耦合绝热动态触发器及其同步时序电路综合方法。首先利用文献[1]的电路三要素理论定量描述交叉耦合型绝热锁存器，由绝热主锁存器和从锁存器构成一个单相输入的绝热触发器。在交叉耦合型绝热触发器的基础上，本文提出绝热同步动态时序电路综合方法，用此法设计出绝热8421BCD码错码检测电路（仅用50管），总功耗小于三个绝热ADL非门的功耗，计算机模拟验证本文方法的正确性。     

异步时序逻辑电路的设计方法探讨

在传统的同步时序电路设计方法的基础上,提出了一种新的异步时序电路的设计方法。该方法直接从时序电路的时序波形图,获得触发器的触发脉冲;根据时钟信号作用下引起的状态转换,填写次态卡诺图。其特点是原理简单,易于理解,使设计更加直观清楚。     

Hybrid Fault Simulation for Synchronous Sequential Circuits

We present a fault simulator for synchronous sequential circuits that combines the efficiency of three-valued logic simulation with the exactness of a symbolic approach. The simulator is hybrid in the sense that three different modes of operation—three-valued, symbolic and mixed—are supported. We demonstrate how an automatic switching between the modes depending on the computational resources and the properties of the circuit under test can be realized, thus trading off time/space for accuracy of the computation. Furthermore, besides the usual Single Observation Time Test Strategy (SOT) for the evaluation of the fault coverage, the simulator supports evaluation according to the more general Multiple Observation Time Test Strategy (MOT). Numerous experiments are given to demonstrate the feasibility and efficiency of our approach. In particular, it is shown that, at the expense of a reasonable time penalty, the exactness of the fault coverage computation can be improved even for the largest benchmark functions.     

Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits

We present a technique to statistically estimate path-delay fault coverage for synchronous sequential circuits. We perform fault-free simulation using a multivalue algebra and accumulate signal transition statistics, from which we calculate controllabilities of all signals and sensitization probabilities for all gates and flip-flops. We use a rated clock testing model where all time frames operate at the rated clock. We obtain path observabilities either by enumerating paths in the all-paths method, or by a nonenumerative method considering only the longest paths. The path-delay fault detectability is the product of observabilities of signals on paths from primary inputs (PIs) or pseudo-primary inputs (PPIs) to primary outputs (POs) or pseudo-primary outputs (PPOs), and the controllability on the corresponding PI or PPI. We use the optimistic update rule of Bose et al. for updating latches during logic simulation. When compared with exact fault simulation, the average absolute deviation in our statistical fault coverage estimation technique is 1.23% and the very worst absolute deviation was 6.59%. On average, our method accelerates delay fault coverage computation four times over an exact path delay fault simulator.     

一种片上系统(SOC)时钟同步设计方法

SoC设计很大程度上依赖于IP核的可重用性。由于各IP核中时钟延时的不同，要将IP核集成到一个同步SoC中时钟分布变得很难。本文介绍了一种SoC时钟同步设计方法，这种方法将可调节延时的时钟电路插入在时钟分布网络中．以取得时钟边沿的匹配和同步。使用可调节电路进行时序调整，减少了设计迭代时间，节约了设计成本。     

一种ECL超高速D触发器的设计与制作

介绍了一种ＥＣＬ超高速Ｄ触发器的电路设计，版图设计及工艺制作。研制中成功地解决了高速度与低功耗的矛盾。电路的工作频率典型值为８５０ＭＨｚ，是高要达９００ＭＨｚ以上，功耗电流典型值为３ｍＡ。     

一种分析模拟电路中互连线的新方法

互连线在高性能模拟集成电路中的影响已变得越来越不可忽视,部分元等效电路法（Partial Element Circuit,PEEC）是一种分析互连线的有效模型,常用方法是再用SPICE等数值模拟软件对PEEC模型进行分析。文中提出的用符号分析法模拟PEEC模型以及其它电路元器件,具有大大降低运算量等优点。基于这一点开发出一套交互式程序,使得包括考虑互连线影响的模拟电路的设计、验证和优化变得更容易、更有效率。     

A New Design Method for Self-Checking Unidirectional Combinational Circuits

In this paper, a new method for the design of unidirectional combinational circuits is proposed. Carefully selected non-unidirectional gates of the original circuit are duplicated such that every single gate fault can only be propagated to the circuit outputs on paths with either an even or an odd number of inverters. Unlike previous methods, it is not necessary to localize all the inverters of the circuit at the primary inputs. The average area over head for the described method of circuit transformation is 16% of the original circuit, which is less than half of the area overhead of other known methods. The transformed circuits are monitored by Berger codes, or by the least significant two bits of a Berger code. All single stuck-at faults are detected by the method proposed.