A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability

This brief describes an adaptive bandwidth bus architecture based on hybrid current/voltage mode repeaters for long global RC interconnect static busses that achieves high-data rates while minimizing the static power dissipation associated with current-mode (CM) signaling. An experimental adaptive bandwidth bus test chip fabricated in AMI 1.6-/spl mu/m Bulk CMOS indicates a reduction in power dissipation of approximately 62% over CM sensing and an increase in maximum data rate of 40% over voltage-mode signaling.     

A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling

This paper describes a differential current-mode bus architecture based on driver pre-emphasis for on-chip global interconnects that achieves high-data rates while reducing bus power dissipation and improving signal delay latency. The 16-b bus core fabricated in 0.25- $mu$m complementary metal–oxide–semiconductor (CMOS) technology attains an aggregate signaling data rate of 32 Gb/s over 5–10-mm-long lossy interconnects. With a supply of 2.5 V, 25.5–48.7-mW power dissipation was measured for signal activity above 0.1, equivalent to 0.80–1.52 pJ/b. This work demonstrates a 15.0%–67.5% power reduction over a conventional single-ended voltage-mode static bus while reducing delay latency by 28.3% and peak current by 70%. The proposed bus architecture is robust against crosstalk noise and occupies comparable routing area to a reference static bus design.      

1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus

A 1.6 Gb/s/pin 4-pulse-amplitude-modulated (PAM) multidrop signaling system has been designed. The motivation for multi-PAM signaling is discussed. The system uses single-ended+reference current-mode signaling with three dc references for maximum bandwidth per pin. A test chip with six I/O pins was fabricated in 0.35-μm CMOS and tested in a 28-Ω evaluation system using on-chip 2¹⁰ pseudorandom bit sequence (PRBS) generator/checkers. Two different 4-PAM transmitter structures were designed and measured. A high-gain windowed integrating input receiver with wide common-mode range was designed in order to improve signal-to-noise ratio when operating with smaller 4-PAM input levels. Gray coding allowed a folded preamplifier architecture to be used in the LSB input receiver to minimize area and power. In-system margins are measured via system voltage and timing shmoos with a master communicating with two slave devices     

1.25 Gb/s低功耗CMOS光接收机限幅放大器

设计并实现了用于光纤用户网和千兆以太网光接收机的限幅放大器。电路采用有源电感负载来拓展带宽、稳定直流工作点 ,通过直接耦合技术来提高增益、降低功耗。测试结果表明 ,在从 5 m Vp- p到 5 0 0 m Vp- p,即40 d B的输入动态范围内 ,在 5 0 Ω负载上的单端输出电压摆幅稳定在 2 80 m Vp- p。在 5 V电源电压下 ,功耗仅为1 30 m W。电路可稳定工作在 1 5 5 Mb/s、62 2 Mb/s、1 .2 5 Gb/s三个速率上。     

一种面向单片DC/DC的低压高效片上电流检测技术

本文提出并实现了一种面向电流模式单片开关DC/DC转换器的低压高效片上电流采样电路.该电路利用功率管等效电阻电流检测技术和无需OP放大器的源极输入差分电压放大技术,使电路的应用范围可低达2.3V;-3dB带宽12MHz;在最大负载电流情况下的静态电流峰值仅19μA,比常规采用功率管镜像电流检测技术的静态电流峰值低1.5个量级左右.转换器基于0.5μm 2P3M Mixed Signal CMOS工艺设计制作.测试结果表明,电流检测电路的最大检测电流1.1A,转换器的输入最低电压2.3V,重负载转换效率高于93%.     

A 1-Gb/s bidirectional I/O buffer using the current-mode scheme

A current-mode bidirectional I/O buffer was designed, and the maximum effective bandwidth of 1.0 Gb/s per wire was obtained from measurements. To enhance the operating speed, the voltage swing on the transmission line was reduced to 0.5 V and the internal nodes of the buffer were designed to be low impedance nodes using the current-mode scheme. An automatic impedance-matching scheme was used to generate bias voltages, which adjust output resistance of the buffer to be equal to the characteristic impedance of the transmission line in spite of process variations. The chip was fabricated by using a 0.8-μm CMOS technology. The chip size was 500×330 μm², and the power consumption was 50 mW at a supply voltage of 3 V     

Current-mode signaling in deep submicrometer global interconnects

This paper addresses propagation delay and power dissipation for current mode signaling in deep submicrometer global interconnects. Based on the effective lumped element resistance and capacitance approximation of distributed RC lines, simple yet accurate closed-form expressions of delay and power dissipation are presented. A new closed-form solution of delay under step input excitation is first developed, exhibiting an accuracy that is within 5% of SPICE simulations for a wide range of parameters. The usefulness of this solution is that resistive load termination for current mode signaling is accurately modeled. This model is then extended to a generalized delay formulation for ramp inputs with arbitrary rise time. Using these expressions, the optimum-line width that minimizes the total delay for current mode circuits is found. Additionally, a new power-dissipation model for current-mode signaling is developed to understand the design tradeoffs between current and voltage sensing. Based on the results and derived formulations, a comparison between voltage and current mode repeater insertion for long global deep submicrometer interconnects is presented.     

2.5Gb/Scmos光接收机跨阻前置放大器

给出了一种利用0.35μm CMOS工艺实现的2.5Gb/s跨阻前置放大器。此跨阻放大器的增益为59 dB*Ω,3dB带宽为2GHz,2GHz处的等效输入电流噪声为0.8×10-22 A2/Hz。在标准的5V电源电压下,功耗为250mW。PCML单端输出信号电压摆幅为200mVp-p。整个芯片面积为1.0mm×1.1mm。     

A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane Communications

A 12-GS/s 8-bit digital-to-analog converter (DAC) enables 24 Gb/s signaling over conventional backplane channels. Designed in a 90-nm CMOS process, the circuit occupies an area of 670 mum times 350 mum and achieves INL and DNL of 0.31 and 0.28LSB, respectively. Measured SNDR and SFDR are 41 dB and 51 dB at 750 MHz and 32.5 dB and 35 dB at 1.5 GHz. Measured SDR and 3-dB bandwidth using 12 GS/s random data are 32 dB and 7.1 GHz, respectively. The power dissipation is 190 mW from 1-V and 1.8-V power supplies.     

Design of a low-power 10 Gb/s Si bipolar 1:16-demultiplexer IC

The design of a low-power Si bipolar 1:16-demultiplexer IC built of 1:4-demultiplexer subcomponents for 10 Gb/s (STM-64) is described. The 1:4-demultiplexers feature an architecture with low component count. Special latches controlled by two clock voltages are used. The 1:16-demultiplexer operates up to 12.5 Gb/s with a power dissipation of only 1.5 W at a single power supply voltage of -3 V     

10-Gb/s limiting amplifier and laser/modulator driver in 0.18-/spl mu/m CMOS technology

A limiting amplifier incorporates active feedback, inductive peaking, and negative Miller capacitance to achieve a voltage gain of 50 dB, a bandwidth of 9.4 GHz, and a sensitivity of 4.6 mV/sub pp/ for a bit-error rate of 10/sup -12/ while consuming 150 mW. A driver employs T-coil peaking and negative impedance conversion to achieve operation at 10 Gb/s while delivering a current of 100 mA to 25-/spl Omega/ lasers or a voltage swing of 2 V/sub pp/ to 50-/spl Omega/ modulators with a power dissipation of 675 mW. Fabricated in 0.18-/spl mu/m CMOS technology, both prototypes operate with a 1.8-V supply.     

Integrated laser-diode voltage driver for 20-Gb/s optical systemsusing 0.3-μm gate length quantum-well HEMT's

An integrated laser-diode voltage driver (LDVD) making use of enhancement/depletion AlGaAs-GaAs quantum-well high electron mobility transistors (QW HEMTs) with gate lengths of 0.3 μm has been developed. Its large signal bandwidth is 12 GHz. Eye diagrams of the output signal at bit rates up to 8 Gb/s show an opening similar to that of the input signal. Supporting material is given indicating that the LDVD might operate at bit rates up to 20 Gb/s. The maximum output current is over 90 mA; the maximum modulation voltage of 800 mV corresponds to 40-mA modulation current for a laser diode with 20-Ω dynamic resistance. The power consumption is less than 500 mW     

A high-speed, low-power bipolar digital circuit for Gb/s LSI's:current mirror control logic

A novel low-power bipolar circuit for Gb/s LSIs, current mirror control logic (CMCL), is described. To reduce supply voltage and currents, the current sources of emitter-coupled-logic (ECL) series gate circuits are removed and the lower differential pairs are controlled by current mirror circuits. This enables circuits with the same function as two-stacked ECL circuits to operate at supply voltage of -2.0 V and reduces the current drawn through the driving circuits for the differential pairs to 50% of the conventional level shift circuits (emitter followers) in ECL. This CMCL circuit achieves 3.1-Gb/s (D-FF) and 4.3-GHz (T-FF) operation with a power supply voltage of -2.0 V and power dissipation of only 1.8 mW/(FF)     

2.5 Gb／s 16：1 MUX IC Design with CMOS

A low--power and high--speed 16.-1 MUX IC designed for optical fiber communication based on TSMC 0.25μm CMOS technology is presented. A tree—type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak—to—peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8mm^2.     

2.5Gb/s 16:1MUX IC Design with CMOS

A low-power and high-speed 16:1 MUX IC designed for optical fiber communication based on TSMC 0.25 μm CMOS technology is presented. A tree-type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak-to-peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8 mm2.     

A circuit design for 2-Gbit/s Si bipolar crosspoint switch LSIs

An 8×8 and an expandable 16×16 crosspoint switch LSI utilizing a new circuit design and super self-aligned process technology (SST-1A) are discussed. The LSIs successfully switched with a bit error rate of less than 10^-9 at 2.5 Gb/s using a 2⁹-1 pseudorandom NRZ sequence. Pulse jitter was limited to less than 80 ps at 1.2 Gb/s by utilizing a small internal voltage swing (225 mV) employing a differential CML cell, including a selector. The LSIs have an ECL-compatible interface, -4-V and -2-V power supply voltages, and a power dissipation of less than 0.9 W for the 8×8 LSI and 2.8 W for the expandable 16×16 LSI     

Noise suppression scheme for gigabit-scale and gigabyte/s data-rateLSI's

In order to reduce the power/ground noise due to the off-chip parasitic inductance and realize gigabit-scale and ultra-high bandwidth large scale integrations (LSI's), this paper proposes two new techniques: (1) a constant-current voltage-down converter (VDC) which reduces the differential mode noise caused by internal peak current in a chip, and (2) a partially inverted data bus architecture which suppresses the common-mode noise caused by driving a large amount of output buffers. The new VDC requires almost constant current through an external V_dd/V_ss pin in spite of an internal large peak current, resulting in the suppression of the inductance induced voltage bounce and oscillation. Using the new VDC, the power/ground noise in a 1-Gb DRAM is reduced to 20% of the conventional one. The new bus architecture reduces the common-mode noise to 1/n by inverting output bus data partially, using only n-1 bit flag signals. Moreover, the modified new bus architecture reduces the noise to 1/2n by using only n bit flag signals. These architectures achieve the ultra-high data transfer rate of 16 GB/s to 32 GB/s     

An asymptotically zero power charge-recycling bus architecture forbattery-operated ultrahigh data rate ULSI's

An asymptotically zero power charge recycling bus (CRB) architecture, featuring virtual stacking of the individual bus-capacitance into a series configuration between supply voltage and ground, has been proposed. This CRB architecture makes it possible to reduce not only each bus-swing but also a total equivalent bus-capacitance of the ultramultibit buses running in parallel. The voltage swing of each bus is given by the recycled charge-supplying from the upper adjacent bus capacitance, instead of the power line. The dramatical power reduction was verified by the simulated and measured data. According to these data, the ultrahigh data rate of 25.6 Gb/s can be achieved while maintaining the power dissipation to be less than 100 mW, which corresponds to less than 10% that of the previously reported 0.9 V suppressed bus-swing scheme, at V_cc=3.6 V for the bus width of 512 b with the bus-capacitance of 14 pF per bit operating at 50 MHz     

LVDS I/O interface for Gb/s-per-pin operation in 0.35-μm CMOS

This paper presents the design and the implementation of input/output (I/O) interface circuits for Gb/s-per-pin operation, fully compatible with low-voltage differential signaling (LVDS) standard. Due to the differential transmission technique and the low voltage swing, LVDS allows high transmission speeds and low power consumption at the same time. In the proposed transmitter, the required tolerance on the dc output levels was achieved over process, temperature, and supply voltage variations with neither external components nor trimming procedures, by means of a closed-loop control circuit and an internal voltage reference. The proposed receiver implements a dual-gain-stage folded-cascode architecture which allows a 1.2-Gb/s transmission speed with the minimum common-mode and differential voltage at the input. The circuits were implemented in a 3.3-V 0.35-μm CMOS technology in a couple of test chips. Transmission operations up to 1.2 Gb/s with random data patterns and up to 2 Gb/s in asynchronous mode were demonstrated. The transmitter and receiver pad cells exhibit a power consumption of 43 and 33 mW, respectively     

A Novel Input-Side Current Sensing Method to Achieve AVP for Future VRs

This paper begins with a review of different current sensing methods for the voltage regulator (VR) to achieve adaptive voltage position (AVP). These methods are either inaccurate or with high power consumption for current sensing. Next, a new input-side current sensing method for AVP is proposed. The basic idea of the proposed method is to sense the average input current, which results in low power dissipation for current sensing. Meanwhile, a compensation circuit is proposed to eliminate current sensing errors due to input and output voltage variations. As a result, both low power dissipation and good current sensing accuracy can be achieved by applying the proposed method. The transient and tolerance analysis of this method are provided and a design guideline is illustrated and experimentally verified.