Novel hydrogen annealing for forming SiO2 film by rapidthermal processing

Hydrogen annealing at 700-1100°C for 0-300 s has been combined with SiO₂ formation by rapid thermal processing (RTP). The SiO₂ films formed with the above processes were evaluated by C-V and I-V measurements and by time-dependent dielectric breakdown (TDDB) tests. These films provide longer time to breakdown andless positive charge generation than SiO₂ films formed without H₂ annealing. In particular, the SiO₂ formation-H₂ annealing SiO ₂ formation process is quite effective in improving the dielectric strength of the thin RTP-SiO₂ film     

Spatial Distributions of Trapping Centers in HfO2/SiO2 Gate Stack

An analysis methodology for charge pumping (CP) measurements was developed and applied to extract spatial distributions of traps in SiO ₂/HfO₂ gate stacks. This analysis indicates that the traps accessible by CP measurements in the frequency range down to a few kilohertz are located primarily within the SiO₂ layer and HfO₂/SiO₂ interface region. The trap density in the SiO₂ layer increases closer to the high-kappa dielectric, while the trap spatial profile as a function of the distance from the high-kappa film was found to be dependent on high-kappa film characteristics. These results point to interactions with the high-kappa dielectric as a cause of trap generation in the interfacial SiO₂ layer     

Two-step annealing technique for leakage current reduction inchemical-vapor-deposited Ta2O5 film

A capacitor technology developed to obtain extremely thin Ta₂ O₅ dielectric film with an effective SiO₂ film thickness down to 3 nm (equivalent to 11 fF/μm²) for a 1.5-V, low-power, high-density, 64-Mb DRAM is discussed. The Ta₂ O₅ has low leakage current, low defect density, and excellent step coverage. The key process is two-step annealing after the deposition of the film by thermal chemical vapor deposition (CVD). The first step involves ozone (O₃) annealing with ultraviolet light irradiation, which reduces the leakage current. The second step is dry oxygen (O₂) annealing, which decreases the defect density. A more significant reduction in the leakage current is attained by the combination of the two annealing steps     

Thin-gate SiO2 films formed by in situ multiple rapidthermal processing

A reliable method of forming very thin SiO₂ films (<10 nm) has been developed by rapid thermal processing (RTP) in which in situ multiple RTP sequences have been employed. Sub-10-nm-thick SiO₂ films formed by single-step RTP oxidation (RTO) are superior to conventional furnace-grown SiO₂ on the SiO₂ /Si interface characteristics, dielectric strength, and time-dependent dielectric-breakdown (TDDB) characteristics. It has been confirmed that the reliability of SiO₂ film can be improved by pre-oxidation RTP cleaning (RTC) operated at 700-900°C for 20-60 s in a 1%HCl/Ar or H₂ ambient. The authors discuss the dielectric reliability of the SiO₂ films formed by single-step RTO in comparison with conventional furnace-grown SiO₂ films. The effects and optimum conditions of RTC prior to RTO on the TDDB characteristics are demonstrated. The dielectric properties of nitrided SiO₂ films formed via the N₂O-oxynitridation process are described     

Electrical properties of low-temperature pyrolytic SiO2on InP

The first application of a new technique (SiH₄+O₂ at 83-330°C and 2-12 torr) for deposition of SiO₂ on InP is reported. SiO₂ deposited at 150-330°C has breakdown strength of 8-10 MV/cm, resistivity >10¹⁵ Ωcm, and refractive index of 1.45-1.46 comparable to thermal SiO ₂ grown at 1100°C. C/V measurements on Al/SiO₂/InP MIS structures suggest that very low temperature oxides (90-100°C) have the best interfacial properties     

Single damascene integration of porous Zirkon™ version 1 low-k dielectric films

Zirkon™ LK2000 version 1 dielectric film (Zirkon™ is a trademark of Shipley Company L.L.C), a porous methylsilsesquioxane (MSQ)-based spin-on dielectric with a k value targeted at 2.0, has been integrated in single damascene structures. For patterning, a dual SiC/SiO₂ CVD hard-mask was used. Surface treatments (DUV ozone (DUV-O₃), plasma treatments) were tested to solve the adhesion issues encountered at the CVD hard-mask and the low-k interface. Adhesion is only improved when plasma treatments are used. Analyses (FTIR, TDS, nano-indentation) show that the plasma treatments only modify the low-k surface. For integration, a plasma treatment (He, NH₃, N₂/O₂) prior to deposition of the CVD hard-mask was included. After patterning, copper metallization and CMP of the wafers, electrical evaluation shows that, compared to the reference wafer (no plasma treatment), plasma-treated wafers have a higher yield and a lower sheet resistance. The RC delay is slightly higher for the plasma-treated wafers than for the reference wafer.     

Novel technique for SiO2 formed by liquid-phasedeposition for low-temperature processed polysilicon TFT

A technique for SiO₂ formation by liquid-phase deposition (LPD) at nearly room temperature for low-temperature processed (LTP) polysilicon thin-film transistor (poly-Si TFT) was developed. LPD SiO₂ film with a lower P-etch rate shows a dense structure. LPD SiO₂ also exhibits good electrical characteristics. LTP poly-Si thin-film transistors (TFTs) with LPD SiO ₂ as the gate insulator have been fabricated and investigated. Their characteristics indicate performance adequate for their use as pixel transistors in liquid crystal displays (LCDs)     

A Comparative Study of HfTaON/SiO2 and HfON/SiO2 Gate Stacks With TaN Metal Gate for Advanced CMOS Applications

The electrical characteristics of a novel HfTaON/SiO₂ gate stack, which consists of a HfTaON film with a dielectric constant of 23 and a 10-Aring SiO₂ interfacial layer, have been investigated for advanced CMOS applications. The HfTaON/SiO₂ gate stack provided much lower gate leakage current against SiO₂ , good interface properties, excellent transistor characteristics, and superior carrier mobility. Compared to HfON/SiO₂, improved thermal stability was also observed in the HfTaON/SiO₂ gate stack. Moreover, charge-trapping-induced threshold voltage V _th instability was examined for the HfTaON/SiO₂ and HfON/SiO₂ gate stacks. The HfTaON/SiO₂ gate stack exhibited significant suppression of the V_th instability compared to the HfON/SiO₂, in particular, for nMOSFETs. The excellent performances observed in the HfTaON/SiO₂ gate stack indicate that it has the potential to replace conventional SiO₂ or SiON as gate dielectric for advanced CMOS applications     

Dielectric deposition process for Cu/SiO2 integration in a dual damascene interconnection architecture

A challenge to integrate Cu in device interconnections is to avoid Cu diffusion into silicon active zone that could seriously damage device performance, and into interlevel dielectric that could induce shorts or degrade dielectric performance. This paper relates the integration of Cu-CVD with SiO₂. Structures studied are SiO₂ deposited on Cu-CVD, and SiO₂/SiN/Cu structure: a thin SiN layer is deposited on Cu before SiO₂ to act as diffusion barrier and as an etch stop during the interconnect structure patterning. Both SiO₂ and SiN dielectric processes are made in plasma-enhanced chemical vapor deposition processes, from SiH₄ precursor with addition of, respectively, N₂O or NH₃. Cu contamination is shown to occur during the dielectric deposition onto Cu, and is enhanced by the fluorine presence in the deposition chamber. Deposition processes were evaluated in order to lower Cu contamination in the dielectric bulk. On an other hand, a noticeable degradation in Cu layer resistance was evidenced after dielectric deposition due to copper contamination during the dielectric deposition process. This issue can be addressed by the optimization of the dielectric deposition process.     

Novel gate dielectric films formed by ion plating forlow-temperature-processed polysilicon TFTs

A novel SiO₂ film formed by ion plating (IP) at room temperature was developed for low-temperature-processed (LTP) (<625°C) polysilicon thin-film transistors (poly-Si TFT's). The IP SiO₂ film is a high-density dielectric with strained bonds, and also a high-performance insulator with low-leakage current and high-breakdown voltage. Poly-Si TFT with IP SiO₂ as a gate insulator shows satisfactory performance     

Effects of growth temperature on TDDB characteristics of N2O-grown oxides

Effects of oxide growth temperature on time-dependent dielectric breakdown (TDDB) characteristics of thin (115 Å) N₂O-grown oxides are investigated and compared with those for conventional O₂-grown SiO₂ films with identical thickness. Results show that TDDB characteristics of N₂O oxides are strongly dependent on the growth temperature and, unlike conventional SiO₂, TDDB properties are much degraded for N ₂O oxides with an increase in growth temperature. Large undulations at the Si/SiO₂ interface, caused by locally retarded oxide growth due to interfacial nitrogen, are suggested as a likely cause of degradation of TDDB characteristics in N₂O oxides grown at higher temperatures     

Planarization of dielectric layers for multilevel metallization

A process to planarize low-pressure chemical-vapor deposition (LPCVD) SiO₂ films formed over the abrupt topography of fine-line (2.0-μm pitch) integrated circuits with two levels of metallization and pillar interconnections has been developed with sacrificial photoresist and plasma etching using response-surface methodology. To produce flat dielectric surfaces with this topography, the ratio of the measured etch rate of photoresist to that of phosphorus-doped SiO₂ must be maintained at ~0.4 (3800 and 9100 Å/min, respectively) with an Ar/CF₄/O₂ high pressure plasma generated in a low radio-frequency etching system     

Fabrication of low dielectric constant materials for ULSImultilevel interconnection by plasma ion implantation

High dose-rate plasma ion implantation (PII) has been utilized to produce low dielectric constant (k) SiO₂ films for high quality interlayer dielectrics. The SiO₂ films are fluorine-doped/carbon-doped by PII with CF₄ plasma in an inductively-coupled plasma (ICP) reactor. It is found that the use of CF ₄ doping results in exceptional dielectric properties which differ significantly from fluorinated SiO₂. The dielectric constant of the SiO₂ film is reduced from 4.1 to 3.5 after 5 minute PII, other electrical parameters such as bulk resistivity and dielectric breakdown strength are also improved     

Oxidized Ta2O5/Si3N4dielectric films on poly-crystalline Si for dRAMs

A dielectric film technology characterized by a novel multilayer structure formed by oxidation of Ta₂O₅/Si₃ N₄ films on polysilicon has been developed to realize high-density dRAMs. The dry oxidation of the Ta₂O₅/Si₃N₄ layers was performed at temperatures higher than 900°C. This film has a capacitance per unit area from 5.5 to 6.0 fF/ μm², which is equivalent to that of a 6.0- to 6.5-nm-thick SiO₂. The leakage current at an effective electric field of 5 MV/cm is less than 10^-9 A/cm². Under such an electric field, the extrapolated time to failure for 50% cumulative failure can be as high as 1000 years     

Nearly White-Light Emission From GaN-Based Light-Emitting Diodes Integrated With a Porous SiO 2 Layer

In this letter, we develop a nearly white-light-emitting device by integrating blue/green emission from a GaN-based light-emitting diode with red emission from a porous SiO₂ layer. The porous SiO ₂ layer was fabricated by a novel process procedure to create Si nanocrystals on top of the n-type GaN layer. Red light is generated from the metal-oxide-semiconductor (Ni-Au-SiO₂ oxide-n-type GaN) structure due to the electron-hole recombination in the Si nanocrystals. The device shows a blue light emission at a low biased voltage and nearly white-light emission (green and red colors) at a bias voltage between 14 and 16 V. Our results show the potential of applying such an integrated structure to white-light illumination     

Ultrathin gate oxide grown on nitrogen-implanted silicon for deepsubmicron CMOS transistors

Nitrogen implantation on the silicon substrate was performed before the gate oxidation at a fixed energy of 30 keV and with the split dose of 1.0×10¹⁴/cm² and 2.0×10¹⁴ /cm². Initial O₂ injection method was applied for gate oxidation. The method is composed of an O₂ injection/N₂ anneal/main oxidation, and the control process is composed of a N₂ anneal/main oxidation. CMOS transistors with gate oxide thickness of 2 nm and channel length of 0.13 μm have been fabricated by use of the method. Compared to the control process, the initial O₂ injection process increases the amount of nitrogen piled up at the Si/SiO₂ interface and suppresses the growth of gate oxide effectively. Using this method, the oxidation retarding effect of nitrogen was enhanced. Driving currents, hot carrier reliability, and time-zero dielectric breakdown (TZDB) characteristics were improved     

Formation of high quality ultrathin oxide/nitride (ON) stackedcapacitors by in situ multiple rapid thermal processing [DRAMcells]

High quality, ultrathin (<30 Å) SiO₂/Si₃ N₄ (ON) stacked film capacitors have been fabricated by in situ rapid-thermal multiprocessing. Si₃N₄ film was deposited on the RTN-treated poly-Si by rapid-thermal chemical vapor deposition (RTCVD) using SiH₄ and NH₃, followed by in situ low pressure rapid-thermal reoxidation in N₂O (LRTNO) or in O₂ (LRTO) ambient. While the use of low pressure reoxidation suppresses severe oxidation of ultrathin Si₃N₄ film, the use of N₂O-reoxidation significantly improves the quality of ON stacked film, resulting in ultrathin ON stacked film capacitors with excellent electrical properties and reliability     

Enhanced hot-carrier degradation due to water-related components inTEOS/O3 oxide and water blocking with ECR-SiO2film

The authors point out that a TEOS/O₃-oxide layer used as an interlevel dielectric enhances hot-carrier degradation of MOSFETs due to the water-related components (water and/or silanols) contained in the layer. This results mainly from enhanced hot-electron trapping in the gate oxide and also from interface-trap generation. By applying an ECR-SiO₂ layer under the TEOS/O₃-oxide layer, tolerance against hot-carrier damage is improved to the level of MOSFETs without the TEOS/O₃ oxide. From ESR measurement results, it is found that the spin density of the ECR-SiO₂ film under the TEOS/O₃ oxide is two orders lower than that of the ECR-SiO ₂ film only. It is suggested that the dangling bonds in the ECR-SiO₂ film effectively trap water diffusing from the water-containing overlayer     

Reactor characterization for a process to etchSi3N4 formed on thin SiO2

A plasma etching process for patterning LPCVD (low-pressure chemical vapor deposition) Si₃N₄ which has been formed on thin thermally grown SiO₂ has been developed and characterized with an Applied Materials 8110 batch system using 100-mm-diameter silicon wafers. To fulfill the primary process objectives of minimal critical dimension (CD) loss (~0.08 μm), vertical profiles after etch, retention of some of the underlying thermal SiO₂, and batch etch uniformity, the reactor has been characterized by evaluating the effects of variation of reactor pressure (15 to 65 mTorr), O₂ concentration by flow rate (30 to 70%) of an O₂/CHF₂ mixture, and DC bias voltage (-200 to -550 V). Analysis of the resulting etch rate, etch uniformity, dimensional, and profile data suggests that satisfactory processing may be achieved at low reactor pressure (~25 mTorr), 50-60% O₂ by flow rate in O₂/CHF₃, and low DC bias (-200 to -250 V)     

Dielectric breakdown mechanism of thin-SiO2 studied bythe post-breakdown resistance statistics

The dielectric breakdown mechanism of SiO₂ has been discussed on the basis of the experimental results of the post-breakdown resistance (R_bd) distribution. We have noticed for the first time that R_bd of SiO₂ in MOS devices is strongly related to the SiO₂ breakdown characteristics such as the polarity dependence or the oxide field dependence of Q_bd. In this paper, we discuss the dielectric breakdown mechanism of SiO₂ from the viewpoint of the statistical correlation between the R _bd distribution, the Q_bd. distribution, and the emission energy just at the SiO₂ breakdown, by changing the stress polarity, stress field, and the oxide thickness. For complete dielectric breakdown, it has been clarified that the R_bd distribution under the substrate electron injection is clearly different from that under the gate electron injection. We have also found that, irrespective of the stress current density, the gate oxide thickness and the stressing polarity, R_bd can be uniquely expressed by the energy dissipation at the occurrence of dielectric breakdown of SiO₂ for the complete breakdown. Furthermore, it has been clarified that R_bd does not depend on the energy dissipation at the occurrence of quasidielectric breakdown