H．264整数DCT的FPGA实现

H.264整数DCT变换算法有助于减少计算复杂度,提高编码速度,进一步提高视频或图像的压缩效率。分析H.264整数DCT变换的快速算法及其实现原理,并提出一种用来具体实现一个4×4块的DCT变换的结构;同时给出用VHDL语言实现4×4块DCT变换的内部模块的源代码和仿真波形。仿真结果表明用该算法可快速实现一个4×4块的整数DCT变换。提出一种切实可行的用于H.264整数DCT变换的结构,该结构可完全用硬件电路快速实现;对于用FPGA实现H.264整数DCT变换做了一次实践性的尝试,对深入理解H.264整数DCT变换及其算法的具体实现具有一定的实践意义。     

H．264／AVC中的整数变换与DCT变换的比较

数字视频技术在通信和广播领域获得了日益广泛的应用,视频信息和多媒体信息在网络中的处理和传输成为当前我国信息化中的热点技术。运动图像专家组和视频编码专家组给出一种更好的标准,确定为MPEG-4标准的第十部分,即H.264/AVC。简述H.264的研究意义及DCT的原理。为了减少运算量,分析H.264中如何对宏块的整数变换,详述H.264的编码变换的方法,给出整数变换方法与传统的DCT的区别和联系,并给出H.264的整数变换方法的快速算法即蝶形算法,这与传统的DCT变换是不同的。     

用于H．264（AVC）逆量化的硬件实现结构

量化运算广泛用于各种视频压缩标准中。本文提出一种用于实现H．264(AVC)文档[1]规定的逆量化硬件实现结构，能对输入的四个参数进行并行处理，能与常用于H．264反变换的快速配合使用。该结构由两个逆量化运算电路并行组成，关键路径(critical path)最多两个加法延时，与反变换组合能实现高效处理。     

H．264编码器中插值运算和整数变换的优化

首先分析了H．264编码器中运算密集的插值和整数变换过程；然后对其进行算法改进和优化，给出整数变换的全零预先判决方法；最后以整数变换为例，使用Intel的MMX技术优化运算密集模块。优化后，测试表明插值运算和整数变换模块运行速度有数倍提高。     

基于PNX1700平台的H.264视频编码器优化实现

文章针对PNX1700多媒体处理芯片的硬件结构和特点,将H.264编码算法移植到PNX1700平台并对运动估计,整数变换进行了改进及优化.实验结果表明,使用文中给出的算法,可以在PNX1700上快速实现H.264编码器,满足了视频实时编解码的要求.     

一种H.264视频编码码率控制方法

根据视频编码线性率失真函数和对H．264整数变换量化方法分析，提出一种适合于H．264编码算法的码率控制算法。先验证线性率失真函数对H．264编码算法的适用性，再通过将H．264整数变换的量化分解为系数校正和统一量化两个步骤实现了线性率失真函数在H．264码率控制中的应用。实验证明，与JVT—G012码率控制算法相比，码率控制的准确性和信噪比均有所提高。     

H.264整数DCT的硬件实现

该文在分析了H.264整数DCT（Discrete Cosine Transform）变换原理的基础上,介绍了一种实现4×4前向整数变换的新算法。该算法较多地运用了矩阵运算,与传统的将一个二维DCT变换转变为两个一维DCT变换相比,省略了转置模块,降低了时钟延时,减少了资源占用,更利于达到基于H.264的视频信号处理的性能要求。根据新的算法编写了verilog程序并在QuartusⅡ8.0软件中进行了仿真并得出结果。     

H.264变换编码与量化原理及优化研究

本文分析了H.264视频编码标准中的整数变换和量化过程。H.264采用从DCT变换演化而来的4×4整数变换,使变换算法复杂度减小,同时消除了浮点运算导致的失配现象。将尺度调整融合在量化过程中,减少乘法次数,使H.264标准相对于以前的编码标准更加有效。同时通过采用SSE2指令,实现H.264变换与量化的优化算法,实验结果表明此算法有效地提高了编码速度。     

基于TMS320C64x DSP的H.264整数变换快速实现方法

基于4×4块的整数变换是H.264的技术亮点之一,介绍了4×4整数变换原理及一种整数变换的快速实现算法.在此基础上提出了一种基于TMS320C64x DSP的整数变换快速实现方法,并着重论述了如何对其进行并行汇编优化,以提高指令的并行度,达到提高程序执行效率的目的,从而提高硬件的可实现性.     

基于TMS320C64系列的H.264的整数变换快速实现

介绍了视频标准H.264中的4×4整数变换原理及一种一维整数变换的快速算法,在此基础上利用Kronecker乘积推导出一种适合于TMS320C64系列的二维整数变换的并行算法,结合TMS320C64系列的VILW和SIMD特点进行了相应的优化,提高了算法的并行度。     

Application Specific Processor Design for H.264 Decoder with a Configurable Embedded Processor

An application specific processor for an H.264 decoder with a configurable embedded processor is designed in this research. The motion compensation, inverse integer transform, inverse quantization, and entropy decoding algorithm of H.264 decoder software are optimized. We improved the performance of the processor with instruction‐level hardware optimization, which is tailored to configurable embedded processor architecture. The optimized instructions for video processing can be used in other video compression standards such as MPEG 1, 2, and 4. A significant performance improvement is achieved with high flexibility. Experimental results show that we could achieve 300% performance for the H.264 baseline profile level 2 decoder.     

A real-time inverse quantised transform for multi-standard with dynamic resolution support

In this paper, a real-time configurable intelligent property (IP) core is presented for image/video decoding process in compatibility with the standard MPEG-4 Visual and the standard H.264/AVC. The inverse quantised discrete cosine and integer transform can be used to perform inverse quantised discrete cosine transform and inverse quantised inverse integer transforms which only required shift and add operations. Meanwhile, COordinate Rotation DIgital Computer iterations and compensation steps are adjustable in order to compensate for the video compression quality regarding various data throughput. The implementations are embedded in publicly available software XVID Codes 1.2.2 for the standard MPEG-4 Visual and the H.264/AVC reference software JM 16.1, where the experimental results show that the balance between the computational complexity and video compression quality is retained. At the end, FPGA synthesised results show that the proposed IP core can bring advantages to low hardware costs and also provide real-time performance for Full HD and 4K–2K video decoding.     

低码率下实时高清视频压缩方案

在低码率的条件下,H.264视频压缩很容易产生失真并且基于这一标准的高清实时编码具有较高复杂度,在硬件中很难实现。提出一种解决方案,在低码率的条件下,可以在TI TMS320C6455 DSP上实现720p@25 f/s高清格式视频的实时编码。该方案通过在整数变换和量化前采取全零块预测方法,同时使用视频抽样、DSP优化和插值处理来降低编码复杂度,达到高速实时压缩的目的。实验结果表明,该方案在低码率下,编码速度能满足实时视频的要求,在客观峰值信噪比指标(PSNR)及人眼视觉特性上都远优于原标准。     

High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard

Video encoding and decoding are computing intensive applications that require high performance processors or dedicated hardware. Video decoding offers a high parallel processing potential that may be exploited. However, a particular task challenges parallelization: entropy decoding. In H.264 and SVC video standards, this task is mainly carried out using arithmetic decoding, an strictly sequential algorithm that achieves results close to the entropy limit. By accelerating arithmetic decoding, the bottleneck is removed and parallel decoding is enabled. Many works have been published on accelerating pure binary encoding and decoding. However, little research has been done into how to integrate binary decoding with context managing and control without losing performance. In this work we propose a FPGA-based architecture that achieves real time decoding for high-definition video by sustaining a 1 bin per cycle throughput. This is accomplished by implementing fast bin decoding; a novel and area efficient context-managing mechanism; and optimized control scheduling.     

Fast 2-dimensional 4 /spl times/ 4 forward integer transform implementation for H.264/AVC

In this paper, the novel two-dimensional (2-D) fast algorithm for realization of 4 /spl times/ 4 forward integer transform in H.264 is proposed. Based on matrix operations with Kronecker product and direct sum, the efficient fast 2-D 4 /spl times/ 4 forward integer transform can be derived from the proposed one-dimensional fast 4 /spl times/ 4 forward integer transform through matrix decompositions. The proposed fast 2-D 4 /spl times/ 4 forward integer transform design doesn't need transpose memory for direct parallel pipelined architecture. The fast 2-D 4 /spl times/ 4 forward integer transform requires fewer latency delays than the state-of-the-art methods. With regular modularity, the proposed fast algorithm is suitable for VLSI implementation to achieve real-time H.264/advanced video coding (AVC) signal processing.     

基于ADSP—BF533的H．264DCT变换及量化的优化实现

根据ITU-T提出的H.264视频编解码标准,对JM算法及TI Blackfin 533 DSP自身特点进行了分析,将标准中编码采用的整数离散余弦变换(DCT)、量化,解码采用的反DCT变换、反量化的JM算法成功移植到DSP上面,同时根据DSP的特点进行软硬件优化,达到了较好效果。     

Fast mode dependent directional transform via butterfly-style transform and integer lifting steps

Mode dependent directional transform (MDDT) can improve the coding efficiency of H.264/AVC but it also brings high computation complexity. In this paper we present a new design for implementing fast MDDT transform through integer lifting steps. We first approximate the optimal MDDT by a proper transform matrix that can be implemented with butterfly-style operation. We further factorize the butterfly-style transform into a series of integer lifting steps to eliminate the need of multiplications. Experimental results show that the proposed fast MDDT can significantly reduce the computation complexity while introducing negligible loss in the coding efficiency. Due to the merit of integer lifting steps, the proposed fast MDDT is reversible and can be implemented on hardware very easily.     

基于H.264预测模式选择的并行算法

针对H.264编码器提出了一种基于线程级别的并行化算法,用于快速RDO模式决策,可以有效地解决H.264编码器帧内模式决策和帧间模式决策之间的数据依赖性,开发出线性级别的并行快速模式决策算法。此外,该方法可以容易地映射到硬件架构,同时采用改进的比特率估计算法和低复杂性的整数失真估计方法。实验结果表明,文中算法减少了总编码时间,降低了运动估计ME的计算开销,同时保持较低的PSNR损失和比特率增加。     

Fast mode decision algorithm for intra prediction in H.264/AVC with integer transform and adaptive threshold

Compared with other existing video coding standards, H.264/AVC can achieve a significant improvement in compression performances. A robust criterion named the rate distortion optimization (RDO) is employed to select the optimal coding modes and motion vectors for each macroblock (MB), which achieves a high compression ratio while leading to a great increase in the complexity and computational load unfortunately. In this paper, a fast mode decision algorithm for H.264/AVC intra prediction based on integer transform and adaptive threshold is proposed. Before the intra prediction, integer transform operations on the original image are executed to find the directions of local textures. According to this direction, only a small part of the possible intra prediction modes are tested for RDO calculation at the first step. If the minimum mean absolute error (MMAE) of the reconstructed block corresponding to the best mode is smaller than an adaptive threshold which depends on the quantization parameter (QP), the RDO calculation is terminated. Otherwise, more possible modes need to be tested. The adaptive threshold aims to balance the compression performance and the computational load. Simulation results with various video sequences show that the fast mode decision algorithm proposed in this paper can accelerate the encoding speed significantly only with negligible PSNR loss or bit rate increment. This work is supported in part by China National Natural Science Foundation (CNSF) under Project No.60572045, the Ministry of Education of China Ph.D. Program Foundation under Project No.20050698033, and by a Cooperation Project (2005.7– 2007.7) with Microsoft Research Asia.