Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-/spl kappa/ dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-/spl kappa/ dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/A(2-5/spl times/10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ to 1.3/spl times/10/sup 19/ cm/sup -3/eV/sup -1/, somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-/spl kappa//gate stacks, relative comparison among them and to the Si--SiO/sub 2/ system.     

High breakdown voltage (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P/InGaAs quasi-enhancement-mode pHEMT with field-plate technology

A high breakdown voltage and a high turn-on voltage (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P/InGaAs quasi-enhancement-mode (E-mode) pseudomorphic HEMT (pHEMTs) with field-plate (FP) process is reported for the first time. Between gate and drain terminal, the transistor has a FP metal of 1 /spl mu/m, which is connected to a source terminal. The fabricated 0.5/spl times/150 /spl mu/m/sup 2/ device can be operated with gate voltage up to 1.6 V owing to its high Schottky turn-on voltage (V/sub ON/=0.85 V), which corresponds to a high drain-to-source current (I/sub ds/) of 420 mA/mm when drain-to-source voltage (V/sub ds/) is 3.5 V. By adopting the FP technology and large barrier height (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P layer design, the device achieved a high breakdown voltage of -47 V. The measured maximum transconductance, current gain cutoff frequency and maximum oscillation frequency are 370 mS/mm, 22 GHz , and 85 GHz, respectively. Under 5.2-GHz operation, a 15.2 dBm (220 mW/mm) and a 17.8 dBm (405 mW/mm) saturated output power can be achieved when drain voltage are 3.5 and 20 V. These characteristics demonstrate that the field-plated (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P E-mode pHEMTs have great potential for microwave power device applications.     

Effect of strain on microwave noise characteristics in In/sub 0.52/Al/sub 0.48/As/In/sub x/Ga/sub 1-x/As (0.53

Chough  K.B. Hong  W.-P. Florez  L. Song  J.I. 《Electronics letters》1993,29(15):1338-1340

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-K dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-K dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/ A(2-5 /spl times/ 10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8 /spl times/ 10/sup 17/ cm/sup -3/ eV/sup -1/ to 1, 3 /spl times/ 10/sup 19/ cm/sup -3/ eV/sup -1/ somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-K/gate stacks, relative comparison among them and to the Si-SiO/sub 2/ system.     

Characteristics of In/sub x/Al/sub 1-x/N-GaN high-electron mobility field-effect transistor

GaN-based field effect transistors commonly include an Al/sub x/Ga/sub 1-x/N barrier layer for confinement of a two-dimensional electron gas (2DEG) in the barrier/GaN interface. Some of the limitations of the Al/sub x/Ga/sub 1-x/N-GaN heterostructure can be, in principle, avoided by the use of In/sub x/Al/sub 1-x/N as an alternative barrier, which adds flexibility to the engineering of the polarization-induced charges by using tensile or compressive strain through varying the value of x. Here, the implementation and electrical characterization of an In/sub x/Al/sub 1-x/-GaN high electron mobility transistor with Indium content ranging from x=0.04 to x=0.15 is described. The measured 2DEG carrier concentration in the In/sub 0.04/Al/sub 0.96/N-GaN heterostructure reach 4/spl times/10/sup 13/ cm/sup -2/ at room temperature, and Hall mobility is 480 and 750 cm/sup 2//V /spl middot/ s at 300 and 10 K, respectively. The increase of Indium content in the barrier results in a shift of the transistor threshold voltage and of the peak transconductance toward positive gate values, as well as a decrease in the drain current. This is consistent with the reduction in polarization difference between GaN and In/sub x/Al/sub 1-x/N. Devices with a gate length of 0.7 /spl mu/m exhibit f/sub t/ and f/sub max/ values of 13 and 11 GHz, respectively.     

Avalanche noise characteristics of single Al/sub x/Ga/sub 1-x/As(0.3

Groves  C. Chia  C.K. Tozer  R.C. David  J.P.R. Rees  G.J. 《Quantum Electronics, IEEE Journal of》2005,41(1):70-75

DC and RF characteristics of E-mode Ga/sub 0.51/In/sub 0.49/P-In/sub 0.15/Ga/sub 0.85/As pseudomorphic HEMTs

The DC and RF characteristics of Ga/sub 0.49/In/sub 0.51/P-In/sub 0.15/Ga/sub 0.85/As enhancement- mode pseudomorphic HEMTs (pHEMTs) are reported for the first time. The transistor has a gate length of 0.8 /spl mu/m and a gate width of 200 /spl mu/m. It is found that the device can be operated with gate voltage up to 1.6 V, which corresponds to a high drain-source current (I/sub DS/) of 340 mA/mm when the drain-source voltage (V/sub DS/) is 4.0 V. The measured maximum transconductance, current gain cut-off frequency, and maximum oscillation frequency are 255.2 mS/mm, 20.6 GHz, and 40 GHz, respectively. When this device is operated at 1.9 GHz under class-AB bias condition, a 14.7-dBm (148.6 mW/mm) saturated power with a power-added efficiency of 50% is achieved when the drain voltage is 3.5 V. The measured F/sub min/ is 0.74 dB under I/sub DS/=15 mA and V/sub DS/=2 V.     

Low frequency noise sources in InAlAs/InGaAs MODFETs

Detailed analysis of the 1/f low-frequency noise (LFN) in In/sub 0.52/Al/sub 0.48/As/InGaAs MODFET structures is performed, for low drain bias (below pinch-off voltage), in order to identify the physical origin and the location of the noise sources responsible for drain current fluctuations in the frequency range 0.1 Hz-10/sup 5/ Hz. Experimental data were analyzed with the support of a general modeling of the 1/f LFN induced by traps distributed within the different layers and interfaces which constitute the heterostructures. Comparative noise measurements are performed on a variety of structures with different barrier (InAIAs, InP) and different channel (InGaAs lattice matched to InP, strained InGaAs, InP) materials. It is concluded that the dominant low frequency noise sources of InAlAs/InGaAs MODFET transistors in the ON state are generated by deep traps distributed within the "bulk" InAlAs barrier and buffer layers. For reverse gate bias, the gate current appears to be the dominant contribution to the channel LFN, whereas both the gate current and the drain and source ohmic contacts are the dominant sources of noise when the device is biased strongly in the ON state. Heterojunction FET's on InP substrate with InP barrier and buffer layers show significantly lower LFN and appear to be more suitable for applications such as nonlinear circuits that have noise upconversion.     

High-temperature thermal stability performance in /spl delta/-doped In/sub 0.425/Al/sub 0.575/As--In/sub 0.65/Ga/sub 0.35/As metamorphic HEMT

We report, to our knowledge, the best high-temperature characteristics and thermal stability of a novel /spl delta/-doped In/sub 0.425/Al/sub 0.575/As--In/sub 0.65/Ga/sub 0.35/As--GaAs metamorphic high-electron mobility transistor. High-temperature device characteristics, including extrinsic transconductance (g/sub m/), drain saturation current density (I/sub DSS/), on/off-state breakdown voltages (BV/sub on//BV/sub GD/), turn-on voltage (V/sub on/), and the gate-voltage swing have been extensively investigated for the gate dimensions of 0.65/spl times/200 /spl mu/m/sup 2/. The cutoff frequency (f/sub T/) and maximum oscillation frequency (f/sub max/), at 300 K, are 55.4 and 77.5 GHz at V/sub DS/=2 V, respectively. Moreover, the distinguished positive thermal threshold coefficient (/spl part/V/sub th///spl part/T) is superiorly as low as to 0.45 mV/K.     

60-GHz high power performance In/sub 0.35/Al/sub 0.65/As-In/sub 0-35/Ga/sub 0.65/As metamorphic HEMTs on GaAs

We report on a double-pulse doped, double recess In/sub 0.35/Al/sub 0.65/As-In/sub 0.35/Ga/sub 0.65/As metamorphic high electron mobility transistor (MHEMT) on GaAs substrate. This 0.15-/spl mu/m gate MHEMT exhibits excellent de characteristics, high current density of 750 mA/mm, extrinsic transconductance of 700 mS/mm. The on and off state breakdown are respectively of 5 and 13 V and defined It gate current density of 1 mA/mm. Power measurements at 60 GHz were performed on these devices. Biased between 2 and 5 V, they demonstrated a maximum output power of 390 mW/mm at 3.1 V of drain voltage with 2.8 dB power gain and a power added efficiency (PAE) of 18%. The output power at 1 dB gain compression is still of 300 mW/mm. Moreover, the linear power gain is of 5.2 dB. This is to our knowledge the best output power density of any MHEMT reported at this frequency.     

Characteristics of In/sub 0.425/Al/sub 0.575/As-InxGa/sub 1-x/As metamorphic HEMTs with pseudomorphic and symmetrically graded channels

In/sub 0.425/Al/sub 0.575/As-In/sub x/Ga/sub 1-x/As metamorphic high electron mobility transistors (MHEMTs) with two different channel designs, grown by molecular beam epitaxy (MBE) system, have been successfully investigated. Comprehensive dc and high-frequency characteristics, including the extrinsic transconductance, current driving capability, device linearity, pinch-off property, gate-voltage swing, breakdown performance, unity-gain cutoff frequency, max. oscillation frequency, output power, and power gain, etc., have been characterized and compared. In addition, complete parametric information of the small-signal device model has also been extracted and discussed for the pseudomorphic channel MHEMT (PC-MHEMT) and the V-shaped symmetrically graded channel MHEMT (SGC-MHEMT), respectively.     

Performance improvement in tensile-strained In/sub 0.5/Al/sub 0.5/As/In/sub x/Ga/sub 1-x/As/In/sub 0.5/Al/sub 0.5/As metamorphic HEMT

This paper proposes a In/sub 0.5/Al/sub 0.5/As/In/sub x/Ga/sub 1-x/As/In/sub 0.5/Al/sub 0.5/As (x=0.3-0.5-0.3) metamorphic high-electron mobility transistor with tensile-strained channel. The tensile-strained channel structure exhibits significant improvements in dc and RF characteristics, including extrinsic transconductance, current driving capability, thermal stability, unity-gain cutoff frequency, maximum oscillation frequency, output power, power gain, and power added efficiency.     

Optimized breakdown probabilities in Al/sub 0.6/Ga/sub 0.4/As-GaAs heterojunction avalanche photodiodes

Recently, it has been shown that the noise characteristics of heterojunction Al/sub 0.6/Ga/sub 0.4/As-GaAs avalanche photodiodes (APDs) can be optimized by proper selection of the width of the Al/sub 0.6/Ga/sub 0.4/As layer. Similar trends have also been shown theoretically for the bandwidth characteristics. The resulting noise reduction and potential bandwidth enhancement have been attributed to the fact that the high bandgap Al/sub 0.6/Ga/sub 0.4/As layer serves to energize the injected electrons, thereby minimizing their first dead space in the GaAs layer. We show theoretically that the same optimized structures yield optimal breakdown-probability characteristics when the APD is operated in Geiger mode. The steep breakdown-probability characteristics, as a function of the excess bias, of thick multiplication regions (e.g., in a 1000-nm GaAs homojunction) can be mimicked in much thinner optimized Al/sub 0.6/Ga/sub 0.4/As-GaAs APDs (e.g., in a 40-nm Al/sub 0.6/Ga/sub 0.4/As and 200-nm GaAs structure) with the added advantage of having a reduced breakdown voltage (e.g., from 36.5 V to 13.7 V).     

547-GHz f/sub t/ In/sub 0.7/Ga/sub 0.3/As-In/sub 0.52/Al/sub 0.48/As HEMTs with reduced source and drain resistance

We fabricated 30-nm gate pseudomorphic channel In/sub 0.7/Ga/sub 0.3/As-In/sub 0.52/Al/sub 0.48/As high electron mobility transistors (HEMTs) with reduced source and drain parasitic resistances. A multilayer cap structure consisting of Si highly doped n/sup +/-InGaAs and n/sup +/-InP layers was used to reduce these resistances while enabling reproducible 30-nm gate process. The HEMTs also had a laterally scaled gate-recess that effectively enhanced electron velocity, and an adequately long gate-channel distance of 12nm to suppress gate leakage current. The transconductance (g/sub m/) reached 1.5 S/mm, and the off-state breakdown voltage (BV/sub gd/) defined at a gate current of -1 mA/mm was -3.0 V. An extremely high current gain cutoff frequency (f/sub t/) of 547 GHz and a simultaneous maximum oscillation frequency (f/sub max/) of 400 GHz were achieved: the best performance yet reported for any transistor.     

Submicron gate Si/sub 3/N/sub 4//AlGaN/GaN-metal-insulator-semiconductor heterostructure field-effect transistors

We present the characteristics of a quarter-micron gate metal-insulator-semiconductor heterostructure field-effect transistor (MISHFET) with Si/sub 3/N/sub 4/ film as a gate insulator. A detailed comparison of the MISHFET and an identical geometry HFET shows them to have the same radio frequency (RF) power gain and cut-off frequency, while the MISHFET has much lower gate-leakage currents and higher RF powers at operating frequencies as high as 26 GHz. The MISHFET gate-leakage currents are well below 100 pA at gate bias values from -10 V to +8 V. At zero gate bias, the drain saturation current is about 0.9 A/mm and it increases to 1.2 A/mm at +8 V gate bias. The output RF power of around 6 W/mm at 40 drain bias was found to be frequency independent in the range of 2 to 26 GHz. This power is 3 dB higher than that from HFET of the same geometry. The intrinsic cutoff frequency is /spl sim/63 GHz for both the HFET and the MISHFET. This corresponds to an average effective electron velocity in the MISHFET channel of 9.9/spl times/10/sup 6/ cm/s. The knee voltage and current saturation mechanisms in submicron MISHFETs and heterostructure field-effect transistors (HFET) are also discussed.     

Gate field emission induced breakdown in power SiC MESFETs

The breakdown mechanism of SiC MESFETs has been analyzed by careful investigation of gate leakage current characteristics. It is proposed that gate current-induced avalanche breakdown, rather than drain avalanche breakdown, is the dominant failure mechanism for SiC MESFETs: thermionic-field emission and field emission are dominant for the ON state (above pinch-off voltage) and the OFF state (below pinch-off voltage), respectively. The effect of Si/sub 3/N/sub 4/ passivation on breakdown voltage has been also investigated. Si/sub 3/N/sub 4/ passivation decreases the breakdown voltage due to higher electric field at the gate edge compared to edge fields before passivation. A reduction in surface trapping effects after passivation results in the higher electric field because the depletion region formed by trapped electrons is reduced significantly.     

Modeling of tunneling currents through HfO/sub 2/ and (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks

We present a physical modeling of tunneling currents through ultrathin high-/spl kappa/ gate stacks, which includes an ultrathin interface layer, both electron and hole quantization in the substrate and gate electrode, and energy band offsets between high-/spl kappa/ dielectrics and Si determined from high-resolution XPS. Excellent agreements between simulated and experimentally measured tunneling currents have been obtained for chemical vapor deposited and physical vapor deposited HfO/sub 2/ with and without NH/sub 3/-based interface layers, and ALD Al/sub 2/O/sub 3/ gate stacks with different EOT and bias polarities. This model is applied to more thermally stable (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks in order to project their scalability for future CMOS applications.     

Low-frequency noise behavior of SiO/sub 2/--HfO/sub 2/ dual-layer gate dielectric nMOSFETs with different interfacial oxide thickness

The low-frequency noise has been studied in nMOSFETs with an HfO/sub 2/--SiO/sub 2/ gate stack, for different thickness of the SiO/sub 2/ interfacial layer (IL). It is observed that the 1/f-like noise in linear operation, is about 50 times higher in the HfO/sub 2/ devices with a 0.8-nm chemical oxide IL, compared with the 4.5-nm thermal oxide reference n-channel transistors. This is shown to relate to the correspondingly higher trap density in the dielectric material. In addition, it is demonstrated that the noise rapidly reduces with increasing thickness of the IL. From the results for a 2.1-nm SiO/sub 2/ IL, it is derived that at a certain gate voltage range, electron tunneling to a defect band in the HfO/sub 2/ layer may contribute to a pronounced increase in the flicker noise.     

Ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on surface-nitrided Ge

We have studied ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on Ge grown by ultrahigh vacuum-reactive atomic-beam deposition and ultraviolet ozone oxidation. Al/sub 2/O/sub 3/-Ge gate stack had a t/sub eq//spl sim/23 /spl Aring/, and three orders of magnitude lower leakage current compared to SiO/sub 2/. HfO/sub 2/-Ge allowed even greater scaling, achieving t/sub eq//spl sim/11 /spl Aring/ and six orders of magnitude lower leakage current compared to SiO/sub 2/. We have carried out a detailed study of cleaning conditions for the Ge wafer, dielectric deposition condition, and anneal conditions and their effect on the electrical properties of metal-gated dielectric-Ge capacitors. We show that surface nitridation is important in reducing hysteresis, interfacial layer formation and leakage current. However, surface nitridation also introduces positive trapped charges and/or dipoles at the interface, resulting in significant flatband voltage shifts, which are mitigated by post-deposition anneals.     

Diamond FET using high-quality polycrystalline diamond with f/sub T/ of 45 GHz and f/sub max/ of 120 GHz

Using high-quality polycrystalline chemical-vapor-deposited diamond films with large grains (/spl sim/100 /spl mu/m), field effect transistors (FETs) with gate lengths of 0.1 /spl mu/m were fabricated. From the RF characteristics, the maximum transition frequency f/sub T/ and the maximum frequency of oscillation f/sub max/ were /spl sim/ 45 and /spl sim/ 120 GHz, respectively. The f/sub T/ and f/sub max/ values are much higher than the highest values for single-crystalline diamond FETs. The dc characteristics of the FET showed a drain-current density I/sub DS/ of 550 mA/mm at gate-source voltage V/sub GS/ of -3.5 V and a maximum transconductance g/sub m/ of 143 mS/mm at drain voltage V/sub DS/ of -8 V. These results indicate that the high-quality polycrystalline diamond film, whose maximum size is 4 in at present, is a most promising substrate for diamond electronic devices.