A backside illuminated 400 × 400 charge-coupled device imager

Large-area backside illuminated charge-coupled device imagers have been fabricated using double level aluminum transfer electrode technology. Devices with 100 × 160 and 400 × 400 resolution elements have been fabricated using buried channel technology for high charge transfer efficiency. Detailed optical characterization has been performed on these imagers over the temperature range -40 to +24°C and at several operating frequencies between 10 kHz and 1 MHz.     

A multi-band CMOS PLL-based frequency synthesizer for DRM/DRM+/DAB systems

A wideband frequency synthesizer is designed and fabricated in a 0.18 μm CMOS technology. It is developed for DRM/DRM+/DAB systems and is based on a programmable integer-N phase-locked loop. Instead of using several synthesizers for different bands, only one synthesizer is used, which has three separated divider paths to provide quadrature 8-phase LO signals. A wideband VCO covers a frequency band from 2.0 to 2.9 GHz, generates LO signals from 32 to 72 MHz, and from 250 to 362 MHz. In cooperation with a programmable XTAL multi-divider at the PLL input and output dividers at the PLL output, the frequency step can be altered from 1 to 25 kHz. It provides an average output phase noise of ?80 dBc/Hz at 10 kHz offset, ?95 dBc/Hz at 100 kHz offset, and ?120 dBc/Hz at 1 MHz offset for all the supported channels. The output power of the LO signals is tunable from 0 dBm to +3 dBm, and the phase of quadrature signals can also be adjusted through a varactor in the output buffer. The power consumption of the frequency synthesizer is 45 mW from a 1.8 V supply.     

A 16 384-bit high-density CCD memory

A 16 384-bit charge-coupled device (CCD) memory has been developed for mass storage memory system application where moderate latency, high data rate and low system cost are required. The chip measures only 3.45 × 4.29 mm²(136 × 169 mil²), fits a standard 16-pin package, and is organized as four separate shift registers of 4096 bits, each with its own data input and data output terminals. A two-level polysilicon gate n-channel process was used for device fabrication. A condensed serial-parallel-serial (CSPS) structure was found to provide the highest packing density. Only two external clocks are required driving capacitances of 60 pF each at one-half the data transfer rate. Operations at data rates of 100 kHz to 10 MHz have been demonstrated experimentally, the on-chip power dissipation at 10 MHz being less than 20 µW/bit.     

一种低抖动低杂散的亚采样锁相环

设计了一个5.156 25 GHz低抖动、低杂散的亚采样锁相环,使用正交压控振荡器产生4路等相位间隔时钟。分析了电荷泵的杂散理论,使用差分缓冲器和互补开关对实现了低杂散。使用Dummy采样器和隔断缓冲器,进一步减小了压控振荡器对杂散的恶化。该亚采样锁相环在40 nm CMOS工艺下实现,在1.1 V的供电电压下,功耗为7.55 mW;在156.25 MHz频偏处,杂散为-81.66 dBc;亚采样锁相环输出时钟的相位噪声在10 kHz~100 MHz区间内积分,得到均方根抖动为0.26 ps。     

A novel low power flip-flop design using footless scheme

A highly compact source follower coupling based low-pass filter (LPF) topology is proposed that synthesizes a 3rd-order low-pass transfer function in a single stage with no use of operational amplifiers. Chopper stabilization technique is utilized to reduce 1/f noise for minimizing the in-band integrated noise. Implemented and simulated in a 0.18 μm CMOS process, the 3rd-order LPF achieves a ??3 dB bandwidth of 20 MHz with a 280 μA total current from a 1.4 V supply voltage, defining a power-per-pole/bandwidth efficiency of 6.5 μW/MHz. The output noise density at low frequencies is largely reduced with chopper stabilization technique. The integrated output noise from 10 kHz to 2 MHz is minimized from 22.47 to 7.04 μV_rms, with a 10.1 dB improvement. The averaged output noise density over the filter bandwidth is 9.4 nV/√Hz, which is mostly contributed by thermal noise of transistors.     

An integrated 8-12 GHz fractional-N frequency synthesizer in SiGe BiCMOS for satellite communications

We present an integrated fractional-N low-noise frequency synthesizer for satellite applications. By using two integrated VCOs and combining digital and analog tuning techniques, a PLL lock range from 8 to 12 GHz is achieved. Due to a small VCO fine tuning gain and optimized charge pump output biasing, the phase noise is low and almost constant over the tuning range. All 16 sub-bands show a tuning range above 900 MHz each, allowing temperature compensation without sub-band switching. This makes the synthesizer robust against variations of the device parameters with process, supply voltage, temperature and aging. The measured phase noise is ?87 dBc/Hz and ?106 dBc/Hz at 10 kHz and 1 MHz offset, respectively. In integer-N mode, phase noise values down to ?98 dBc/Hz at 10 kHz and ?111 dBc/Hz at 1 MHz offset, respectively, were measured.     

Relative frequency stability of stable He-Ne gas laser structures

Enhanced He-Ne gas laser stability has been achieved by constructing the mirror and gas discharge tube as an integral unit. The primary components are made from Corning ULE and 99JJW ultralow thermal expansion materials; ultrahigh-vacuum-type materials are used throughout. The ambient pressure sensitivity of these 6328-Å laser structures is 2.5 MHz/torr. Preliminary beat frequency measurements between two lasers, under pressure and temperature-controlled conditions, have yielded a beat frequency spectral width of the order of 2 kHz over an interval of 1 s. This result was achieved without the use of any elaborate sound or vibration isolation. Improved isolation reduced the spectral width to 100 Hz for a measurement duration of 0.02 s. The single-structure mirror-discharge tube has provided relative output power stabilities of better than 3 parts in 1000 over a period of 12 h. The frequency-modulation sensitivity is 1.2 kHz/μA of discharge current, from dc to 100 kHz.     

Radio-frequency hazards in the VLF to MF band

The body currents induced in a human in conductive contact with various ungrounded metallic objects like cars, trucks, fences, etc., are calculated for the frequency band 10 kHz to 10 MHz. The calculated incident E-fields required to produce thershold perception and let-go currents indicate that the recently proposed ANSI guideline of 100 mW/cm²(∼615 V/m) in the frequency band 0.3 to 3.0 MHz may result in a potential for RF burns.     

AN ANTI-ALIASING FILTER FOR ∑△ ADC

An anti-aliasing filter for ΣΔ ADCs using a combination of active RC and analog FIR filters is presented in this letter. The first order active RC filter is set at 100kHz to minimize the die size and variations of linear phase and gain in 0–4kHz passband. The 2-tap FIR filter provides more than −53dB attenuation at 2MHz ±4kHz frequency range. The proposed filter achieved more than −76dB attenuation at sampling frequency with ±0.01° phase linearity and ±0.02dB gain variation within 0–4kHz bandwidth. The active die area of the fully differential filter is 0.17mm² in 0.5μm CMOS technology. The experimental and simulation results have been obtained and the feasibility of the proposed method is shown. Supported by Foundation for University Key Teacher by the Ministry of Education of China     

一种用于短距离无线通信并集成频率合成器的多模式多频带发射机

A reconfigurable multi-mode direct-conversion transmitter(TX) with integrated frequency synthesizer(FS) is presented. The TX as well as the FS is designed with a flexible architecture and frequency plan, which helps to support all the 433/868/915 MHz ISM band signals, with the reconfigurable bandwidth from 250 kHz to 2 MHz. In order to save power and chip area, only one 1.8 GHz VCO is adopted to cover the whole frequency range. All the operation modes can be regulated in real time by configuring the integrated register-bank through an SPI interface. Implemented in 180 nm CMOS, the FS achieves a frequency coverage of 320-460 MHz and 620- 920 MHz. The lowest phase noise can be -107 dBc/Hz at a 100 kHz offset and -126 dBc/Hz at a 1 MHz offset. The transmitter features a C10:2 dBm peak output power with a C9:5 dBm 1-dB-compression point and 250 kHz/500 kHz/1 MHz/2 MHz reconfigurable signal bandwidth.     

用于434/868MHz FSK/OOK CMOS发射机的锁相环设计

一种可输出434/868MHz信号的Σ-Δ分数分频锁相环在0.35μmCMOS工艺中集成。该发射机系统采用直接调制锁相环分频比的方式实现FSK调制,OOK的调制则通过功率预放大器的开-关实现。为了降低芯片的成本和功耗,发射机采用了电流数字可控的压控振荡器(VCO),以及片上双端-单端转换电路,并对分频器的功耗设计进行研究。经测试表明,锁相环在868MHz载波频偏为10kHz、100kHz和3MHz处的相位噪声分别为-75dBc/Hz、-104dBc/Hz和-131dBc/Hz,其中的VCO在100kHz频偏处的相位噪声为-108dBc/Hz。在发送模式时,100kHz相邻信道上的功率与载波功率之比小于-50dB。在直流电压2.5V的工作条件下,锁相环的电流为12.5mA,包括功率预放大器和锁相环在内的发送机总面积为2mm2。     

基于单片机控制的频率综合器设计

以ADF4360芯片为核心,设计实现了频率综合器作为1.95 GHz一次变频超外差射频接收机的本振部分,并制作了单片机控制电路。经测试,可以在1.6GHz～1.95GHz范围内以0.5MHz为步长调节输出本振信号频率。在频率为1.9GHz时,相位噪声为-68dBc/Hz（1kHzoffset）、-71dBc/Hz（10kHz offset）、-110dBc/Hz（100kHz offset）、-115dBc/Hz（1MHz off-set）。频率偏差小于50kHz。     

A 100-MHz bandpass sigma-delta modulator with a 75-dB dynamic range for IF receivers

A fourth-order switched-capacitor bandpassΣ△modulator is presented for digital intermediatefrequency (IF) receivers.The circuit operates at a sampling frequency of 100 MHz.The transfer function of the resonator considering nonidealities of the operational amplifier is proposed so as to optimize the performance of resonators.The modulator is implemented in a 0.13-μm standard CMOS process.The measurement shows that the signal-to-noise-and-distortion ratio and dynamic range achieve 68 dB and 75 dB,respectively,over a bandwidth of 200 kHz centered at 25 MHz,and the power dissipation is 8.2 mW at a 1.2 V supply.     

A low power tunable Gm–C filter based on double CMOS inverters in 0.35?μm

In this article, an inverter based transconductor using double CMOS pair is proposed for implementation of a second order lowpass G_m?CC Filter. The proposed operational transconductance amplifier (OTA) and biquad filter are designed using standard 0.35???m CMOS technology. Simulation results demonstrate the central frequency tunability from 10?kHz to 2.8?MHz which is suitable for the wireless specifications of Bluetooth (650?kHz), CDMA 2000 (700?kHz) and Wideband CDMA (2.2?MHz) applications. The power consumption of the filter is 445?nW and 178???W at 10?kHz and 2.8?MHz from 3.3?V supply voltage, respectively. The active area occupied by the designed filter on the silicon is 215?×?720???m². The proposed approach guarantees the upper bound on THD to be ?40?dB for 300?mVpp signal swing. Employing the double CMOS pair in the inverters causes PSRR to reach 68.6?dB which is higher than similar works.     

Antenna design strategy and demonstration for software-defined radio (SDR)

Antennas are a key enabling technology for software-defined radio (SDR). Although software is extremely flexible, SDR??s potential is limited by antenna size and performance. In this paper, we review typical antenna miniaturization techniques and fundamental theories that limit antenna size and performance including operational bandwidth, gain (or range), and radiation pattern. Possible antenna design strategies are discussed to meet the desired specifications in SDR based on observations from the limit theories. The application of strategies to enable multiband (resonant), continuous multiband (frequency independent), and instantaneous, ultra-wideband antennas are discussed qualitatively. Advantages, disadvantages, and design trade-off strategies for different types of antennas are compared from a system-level perspective. A design example for a compact ultra-wideband (UWB) antenna is presented for a software-defined platform. The example involves a direct-conversion radio developed in Wireless@VT that uses a Motorola RFIC having a 100 MHz?C6 GHz operational frequency range with a 9 kHz?C20 MHz channel bandwidth. The example antenna covers frequencies from 450 MHz to 6 GHz instantaneously with approximately 5-dBi realized gain over a finite-size ground plane, including return loss and omni-directional coverage.     

L/S/C波段低相噪、单片锁相频率源实现

介绍一种在20 mm×20 mm PCB上实现L/S/C波段频率源的方法,当频率最高达4 820 MHz时,相位噪声达到-100 dBc/Hz@10 kHz。当步进设为2 MHz,环路带宽为100 kHz时,杂波抑制＞40 dBc,跳频时间＜200 μs;环路带宽为40 kHz时,杂波抑制＞60 dBc,跳频时间＜600 μs。可以应用于一些低端的接收机和校正源上,或是对杂散抑制要求不高的射频通信中。     

超宽带低噪声放大器的计算机辅助设计

叙述了超宽带低噪声放大器的计算机辅助设计方法，提出了利用普通微带混合集成电路．工艺设计超宽带低噪声放大器的方法和关键技术，并且用带封装的ＢＪＴ和ＦＥＴ实现了两个超宽带低噪声放大器。实验结果和设计结果吻合较好。一个利用２ＳＣ３３５８，放大器为三级，频带为３０ｋＨＺ～１６００ＭＨＺ，增益Ｇ＝２０±１ｄＢ，噪声系数ＮＦ≤３．５ｄＢ；另一个利用ＡＴＦ１０２３５（６），放大器为二级，频带为５００ｋＨＺ～６０００ＭＨＺ，增益Ｇ＝２０±２ｄＢ，噪声系数ＮＦ≤２ｄＢ。     

Development of Broad Band VCO at Ka-Band

A broad band VCO has been developed at Ka-band for FMCW Radar applications. To achieve a wide range of frequency variation, VCO has been designed in series configuration. Design steps have been presented. VCO exhibits a tuning range of 600 MHz with the power output of 50 mw, when the controlled varactor voltage varies from 7.5 volts to 15 volts. Frequency drift with temperature has been contained within 30 MHz using a proportionally controlled DC heater module over the temperature range of 0°C to +55°C. Phase Noise of the oscillator measured at the mid and extreme frequencies is about -70 dBc/kHz at 10 kHz away from the carrier. The experimental circuit and measured performance is also presented.     

A high-linearity 50-Ω CMOS differential driver for ISDNapplications

A CMOS differential line-driver amplifier that uses positive feedback in the input stage to give transconductance multiplication and pole-zero doublet insertion is reported. The gain-bandwidth product at 60 kHz is 30 MHz and the unity-gain frequency is 2.7 MHz. The circuit operates from a single 5-V power supply and can achieve a total harmonic distortion (THD) of -78 dB for a 6-V_pp differential output signal at 40 kHz and for a load of 100 Ω and/or 150 pF. For the same measuring condition but with a load of 50 Ω and/or 150 pF, the THD is -73 dB. A power supply rejection of more than 76 dB up to 150 kHz was obtained. The chip occupies an area of 1200 mil² in a 1.5-μm CMOS technology and dissipates 20 mW     

电流模集成电抗元件与频率变换电路的设计

为了拓宽电流模单元电路结构在低压低功耗射频集成电路中的应用,研究把第二代电流传输器用作电抗器件和频率变换电路。以第二代电流传输器为核心,辅助予外围电路,构造从输入到输出端口不同性质传输阻抗的有源电容倍增器和有源电感,并且基于第二代电流传输器组合结构差异的分析,设计了集成频率变换电路。从理论上,推出有源电容倍增器和有源电感结构的合理性。仿真集成频率变换电路,结果袁明对40MHz以下正弦波倍频功能正确,且以100kHz正弦波为调制信号和以10MHz的正弦波为载波获得了双边带调幅信号。这为射频集成电路设计提供了新的思路。