The role of electron traps on the post-stress interface trapgeneration in hot-carrier stressed p-MOSFETs

The generation of interface traps in p-MOSFETs subjected to hot-electron injection is found to proceed even after the stress has been terminated. The extent of post-stress interface trap generation is strongly dependent on the magnitude of the preceding hot-electron stress, as well as the magnitude and polarity of the gate voltage during relaxation. Trap generation is enhanced for negative gate voltage anneal, but suppressed for positive gate voltage anneal. For a given stress-induced damage, the corresponding trap generation kinetics can be completely described by a single characteristic, which is shifted in time according to the magnitude of the applied gate voltage. Existing interface trap generation models are discussed in the light of the experimental results. A new model involving the tunneling of holes from the inversion layer to deep-level electron traps is proposed. Similar post-stress effect observed for hot-electron stressed n-MOSFETs provides additional support for the model. Our work suggests that near-interface electron traps, apart from the well-known hole traps, may also significantly affect the long-term stability of the Si-SiO₂ interface     

Excess currents induced by hot hole injection and FN electroninjection in thin SiO2 films

The behavior of excess currents induced by Fowler-Nordheim electron injection stress (FN electron injection) has been investigated for 6.0-nm oxides. Excess currents are induced by FN electron injection in 6.0-nm oxides together with positive charges being induced in it. To clarify the role of hole injection in FN electron injection, the behavior of excess currents induced by substrate hot hole injection has also been investigated in 6.0-nm oxides. The leakage behavior after hot hole injection is the same as FN electron injection. The excess currents induced both by the FN electron injection and by the substrate hot hole injection are due to trap-assisted tunneling and field enhancement at the cathode due to the positive trapped charge. The charge centroid of the positive charges induced by both stresses are located 3.0 nm from the Si/SiO₂ interface which is at the center of 6.0-nm oxide. The excess currents induced by hot hole injection and FN electron injection are caused by traps in SiO₂ films produced by injected holes from the anode     

AC versus DC hot-carrier degradation in n-channel MOSFETs

The origins of the enhanced AC hot-carrier stress damage are examined. The enhancement in hot-carrier stress damage under AC stress conditions observed with respect to damage under DC stress conditions can fully be explained by the presence of three damage mechanisms occurring during both DC and AC operation: interface states created at low and mid-gate voltages, oxide electron traps created under conditions of hole injection into the oxide, and oxide electron traps created under conditions of hot-electron injection. It is shown that the quasi-static contributions of these mechanisms fully account for hot-carrier degradation under AC stress. The AC stress model is applied to devices from several different technologies and to several different AC stress waveforms. Excellent agreement is obtained in each case. The results demonstrate the validity of the model for frequencies up to 1 MHz. The absence of any transient effect indicates that the model could be applicable at much higher frequencies     

Hole trapping and trap generation in the gate silicon dioxide

Oxide breakdown has been proposed to be a limiting factor for future generation CMOS. The breakdown is caused by defect generation in the oxide. Although electron trap generation has received much attention, there is little information available on the hole trap generation. The relatively high potential barrier for holes at the oxide/Si interface makes it difficult to achieve a high level of hole injection. Most previous work was limited to an injection level Q_inj of 10¹⁴ cm^-2. In this paper, we investigate the hole trapping and trap generation when Q_inj reaches the order of 10¹⁸ cm^-2. When Q_inj <10¹⁵ cm^-2, the trapping is dominated by the as-grown traps. As Q_inj increases further, however, it is found that the generation of new traps controls the trapping. The trap generation does not saturate up to the oxide breakdown. The trapping kinetics for both the as-grown and the generated traps is studied. The relationship between the density of generated traps and the Q_inj is explored. Attention is paid to how the trapping and trap generation depends on the distance from the interface. In contrast to the uniform generation of electron traps across the oxide, we found that the hole trap generation was not uniform and it moved away from the interface as Q_inj increased     

MOSFET degradation due to stressing of thin oxide

Oxide and interface traps in 100 Å SiO2created by Fowler-Nordheim tunneling current have been investigated using capacitor C-V, I-V, and transistor I-V measurements. The net oxide trapped charge is initially positive due to hole trapping near the anode interface and, at sufficiently high fluence, it becomes negative due to the trapping of electrons with a centroid of 60 Å from the injector (cathode) interface. Interface traps (Surface states) are created by tunneling electrons flowing to and from the substrate. The interface-trap energy distribution gives a distinct peak at 0.65 eV above the valence band edge. The positive charge trapping and interface traps generation saturate at high electron fluence, but not the electron trap generation. The generation rates for electron traps and interface traps are weak functions of tunneling current density over the range tested. The interface traps cause degradations in subthreshold current slope and surface electron mobility. The threshold-voltage shift can be either positive or negative under the combined influence of the oxide charges and the interface charges.     

Base current relaxation transient in reverse emitter-base biasstressed silicon bipolar junction transistors

The base current relaxation transient following reverse emitter-base (EB) bias stress and its effect on time-to-failure (TTF) determination are examined in self-aligned and nonself-aligned silicon bipolar junction transistors (BJTs) with thermal and deposited base oxide. A quantitative model indicates that the transient is due to a reduction of the stress-generated positive charge trapped in the oxide layer near the emitter-base junction due to holes tunneling from oxide hole traps to silicon band states or SiO₂/Si interface traps. The neutral oxide hole traps may be quickly recharged through hole tunneling or hole injection into the oxide during further reverse-bias stress. A delay time of ~10^-3 s was observed after the termination of stress before base current relaxation begins, which affects the extraction of the ac operation TTF from dc stress measurements     

The role of electron trap creation in enhanced hot-carrierdegradation during AC stress [n-channel MOSFET]

Enhanced AC degradation during gate voltage transients is shown to be related to neutral electron traps created at low gate voltages under conditions of hole injection and filled at high gate voltages under conditions of electron injection. During DC stress, where interface state damage dominates, electron trap damage is not seen because the created traps are neutral. In experiments where inductive ringing is eliminated, AC degradation rates are independent of the type of edge (falling versus rising) and independent of the rise/fall time     

Hole traps in silicon dioxides. Part I. Properties

As the downscaling of gate oxides continues, trap density in the oxide bulk will reduce, but positive charges formed near to the SiO/sub 2//Si interface become relatively important. For gate oxides used in industry, hole trapping is the most important process for positive charge formation. Apart from as-grown hole traps, we recently reported that new hole traps were generated by electrical stresses. Information on these hole traps, however, is still limited. In part I of this work, properties of both generated and as-grown hole traps are investigated. For the first time, it will be clearly shown that generated hole traps consist of two components; cyclic positive charges (CPC) and antineutralization positive charges (ANPC). The charging and discharging rates of CPC are similar, while the neutralization of ANPC is much more difficult than its charging. Differences between them are also observed in generation kinetics and dependence on measurement temperature. Efforts will be made to explain their differences in terms of energy levels and to link them with positive charges reported in earlier works. We will also show that as-grown traps, regardless their distance from the interface, are not responsible for either ANPC or CPC. This is to say that generated hole traps are not the same as as-grown traps and their differences will be highlighted. In part II, hole trap generation mechanisms will be investigated.     

Hole trap generation in the gate oxide due to plasma-inducedcharging

The paper presents results of hole trapping studies in-thin gate oxide of plasma damaged MOS transistors. Process-induced damage was investigated with antenna test structures to enhance the effect of plasma charging. In addition to neutral electron traps and passivated interface damage, which are commonly observed plasma charging latent damage, we observed and identified hole traps, generated by plasma stress. The amount of hole traps increases with increasing antenna ratio, indicating that the mechanism of hole trap generation is based on electrical stress and current flow, forced through the oxide during plasma etching. The density of hole traps in the most damaged devices was found to be larger than that in reference, undamaged devices by about 100%     

Defect structure and generation of interface states in MOS structures

The correlation between the defect structure of the SiO₂ and the generation of interface traps upon avalanche injection of electrons and holes in MOS capacitor was investigated. Using samples with widely varying densities of intrinsic and H₂O-related trapping centers, and with different oxide thicknesses and gate electrodes it was established from experiments around room temperature that a one to one correlation between the densities of captured carriers and generated interface states exists as long as only a single type of carrier is involved. If simultaneously the second type of carrier is injected the picture becomes more complex. We confirm reports by other authors that at reduced temperatures (typically 77 K) two steps may be distinguished in the generation process, one of which is thermally activated. In this case the “yield” of interface states drops to values distinctly below one, even after warm up. In many cases the energy distribution of the states shows characteristic features: at E = E_v + 0.45 eV for electron injection in samples with H₂O related traps, at E = E_v + 0.75 eV for hole injection. Samples exhibiting these features always show the occurrence of slow states.     

The generation and characterization of electron and hole trapscreated by hole injection during low gate voltage hot-carrier stressingof n-MOS transistors

Hot-carrier stressing carried out on conventional and MDD n-MOS transistors under low gate voltage conditions (V_g⩽V_d/4) is discussed. Following the stress, the devices were subjected to short alternate phases of electron and hole injection into the oxide in order to identify the damage species generated. It is shown that the damage created consists principally of hole and electron oxide traps. This is confirmed using the charge pumping technique. Maximum damage is obtained for conditions of maximum hole injection, indicating that hot holes are responsible for both types of defects. Comparison with maximum interface state damage shows that degradation due to electron traps can be significantly greater than interface state creation in the stressing of n-MOS devices at high drain voltages. The damage is shown to be localized. Two-dimensional simulation of localized charge placed close to the drain junction suggests that equal quantities of positive and negative charge might be created by this stressing. Measurements of capture cross sections for electron trapping reveal two cross sections, σ(1)≈3×10^-15 and σ(2)≈3×10^-16 cm²     

Hot hole induced interface state generation and annihilation in SOIMOSFETs

The effects of pure hot hole injection in SOI MOSFET's are investigated. Pure hot hole injection is achieved by exploiting the opposite channel based carrier injection phenomenon. It is found that significant amounts of interface states are generated, some of which are annihilated by a subsequent hot electron injection pulse. A power law of the form D_it(t)=Ktⁿ with n close to 0.25 was obtained, indicating a more complex, diffusion limited, electrochemical reaction at the interface than previously reported     

Two-dimensional numerical simulation of side-gating effect in GaAsMESFETs

Two-dimensional device simulations that confirm that the side-gating effect in GaAs MESFETs occurs on semi-insulating substrates containing hole traps are discussed. A negative voltage applied on a side gate, a separate n-type doped region, causes an increase in the thickness of the negatively charged layer at the FET channel interface in the substrate, through hole emission from hole traps. The FET channel current is modulated by the electron depletion of the n-type channel, which results from the compensation for the extension of the negatively charged layer at the n-i interface into the i-substrate containing hole traps. The magnitude of the drain current reduction is determined by the total acceptor concentration in the substrate and the donor concentration of the channel. However, the magnitude is independent of the side-gate distances     

Numerical simulation of the response of substrate traps to a voltage applied to the gate of a gallium arsenide field effect transistor

We report on a numerical simulation of the response of substrate traps to a voltage applied to the gate of a gallium arsenide field effect transistor (GaAs FET) using proprietary simulation software. The substrate is assumed to contain shallow acceptors compensated by deep levels. The ratio between the densities of deep and shallow levels is considered to be one hundred, which is a typical value for semi-insulating substrates. Although several traps may be present in the substrate but only the most commonly observed ones are considered, namely hole traps related to Cu and Cr, and the familiar native electron trap EL2. The current–voltage characteristics of the GaAs FET are calculated in the absence as well as in the presence of the above mentioned traps. It was found that the hole traps are affected by the gate voltage while the electron trap is not. This effect on the response of hole traps is explained by the fact that the quasi-hole Fermi level in the substrate is dependent on the gate voltage. However, the electron quasi-Fermi level in the substrate is insensitive to the gate voltage and therefore electron traps are not perturbed.     

Dynamic stress experiments for understanding hot-carrierdegradation phenomena

The results of inhomogeneous hot-carrier injection experiments in which static and dynamic stresses are applied to n-MOSFETs are presented. A qualitative model in which holes play a key role for the final formation of interface states is developed. The holes are injected and trapped within the strained oxide region. The hole-injection process is controlled by hole traps in the oxide, close to the interface. With this model, a large number of dynamic and static hot-carrier stress experiments are consistently explained. Finally, a simple method by which the lifetime of a device under real operation can be predicted from dynamic stress experiments is given     

Hot-carrier memory effect in an Al/SiN/SiO2/Si MNOS diode due to electrical stress

An Al/SiN(70 Å)/SiO2(126 Å)/(p)Si MNOS diode was fabricated by using the LOCOS process. The interface trap densities at SiN-SiO2and at the SiO2-Si interface were measured by a CV method. Successive stresses of biasing at -20 V introduces both trap densities. Memory effect of the flat-band shifts was observed. The electron traps were first produced at the SiN-SiO2interface. In addition, the hole traps were also produced owing to the two-step barrier formation in the insulators. Fowler-Nordheim tunneling may be responsible for the trapping in the oxide. The hole traps can be annealed while the electron traps cannot be.     

SiO2 gate insulator defects,spatial distributions,densities, types,and sizes

Standard IC processes, as well as those involving the use of ionizing radiation, such as x-ray lithography etc., result in the generation of bulk defects, and interface states in the gate insulator, or underlying substrate, respectively, of insulated gate field effect transistors. Bulk defects are believed to be present as positively and negatively charged electron and hole traps, respectively, as well as neutral hole and “large” and “small” neutral electron traps. This paper provides a perspective of the current state of knowledge about the spatial distributions of large bulk defects, their areal densities, sizes, possible interrelationships among them, and the special cases of defects created by ion implanted silicon and oxygen, where knock-on effects have been simulated. It appears that bulk defects may all have their origin in neutral hole traps, (so-called E′ centers) and that when the insulator thickness is decreased to about 6-7 nm, defects are either no longer present, or, more likely, are incapable of trapping charge at room temperature because trapped carriers can either tunnel to one of the interfaces, or be annihilated by a reverse process. It appears possible also that the precursor of the several types of defects only forms at a “grown” silicon-silicon oxide interface. In theory, this would make it possible to grow defect free insulators by a combination of deposition and oxidation processes.     

A coupled study by floating-gate and charge-pumping techniques ofhot carrier-induced defects in submicrometer LDD n-MOSFET's

The creation of defects by hot-carrier effect in submicrometer (0.85-μm) LDD n-MOSFETs is analyzed by the floating-gate and the charge-pumping techniques. It is emphasized that the floating-gate technique is an attractive tool for characterizing the oxide traps located in the drain-gate overlap region, near the oxide spacer of the LDD structures. This work gives new insight into the creation of acceptorlike oxide traps which are electrically active only after electron injection phases. These defects are generated in the whole stress gate bias range (from V_d/8 to V_d) by hot-hole and/or hot-electron injections, and their generation rates (10^-9 and 10^-2 for electron and hole injections, respectively) are one decade greater than for the interface state generation. Two-dimensional simulations show that they are mainly responsible for the I_d-V_g degradation of the LDD MOSFETs, and that the trap concentrations deduced from charge-pumping experiments are consistent with the I _d-V_g degradation     

Radiation damage and its effect on hot-carrier induced instability of 0.5 μm CMOS devices patterned using synchrotron x-ray lithography

The device characteristics and the radiation damgae ofn-channel andp-channel MOSFETs patterned using synchrotron x-ray lithography are examined. The effect of radiation damage caused by x-ray lithography on the device reliability during hot electron injection is investigated. In addition to neutral traps, large amounts of positive oxide charge and interface states, particularly acceptor-like interface states, which cause degradation of MOSFET characteristics are found to be created by x-ray irradiation during the lithography process. Although several annealing steps are performed throughout the entire fabrication process, the radiation damage, particularly neutral traps, is not completely annealed out. The hot-electron induced instability inp-channel MOSFETs is significantly increased due to the enhanced electron trapping in the oxide by residual traps. The effect of radiation damage on hot electron induced instability is found to be more severe inn ⁺-poly buried-channelp-MOSFETs than inp ⁺-poly surface-channel p-MOSFETs. However, the degradation inn-channel MOSFETs due to channel hot carriers is not significantly increased by x-ray lithography. These results suggest that the major degradation mechanism due to hot-carrier inp-channel MOSFETs is electron trapping and inn-channel MOSFETs is interface state generation. It also suggests thatp-channel MOSFETs, in addition ton-channel MOSFETs, needs to be carefully examined in terms of hot carrier induced instability in CMOS VLSI circuits patterned using x-ray lithography.     

Mechanisms of interface trap-induced drain leakage current inoff-state n-MOSFET's

An interface trap-assisted tunneling and thermionic emission model has been developed to study an increased drain leakage current in off-state n-MOSFET's after hot carrier stress. In the model, a complete band-trap-band leakage path is formed at the Si/SiO₂ interface by hole emission from interface traps to a valence band and electron emission from interface traps to a conduction band. Both hole and electron emissions are carried out via quantum tunneling or thermal excitation. In this experiment, a 0.5 μm n-MOSFET was subjected to a dc voltage stress to generate interface traps. The drain leakage current was characterized to compare with the model. Our study reveals that the interface trap-assisted two-step tunneling, hole tunneling followed by electron tunneling, holds responsibility for the leakage current at a large drain-to-gate bias (V_dg). The lateral field plays a major role in the two-step tunneling process. The additional drain leakage current due to band-trap-band tunneling is adequately described by an analytical expression ΔI_d=Aexp(B_it/F). The value of B_it about 13 mV/cm was obtained in a stressed MOSFET, which is significantly lower than in the GIDL current attributed to direct band-to-band tunneling. As V_dg decreases, a thermionic-field emission mechanism, hole thermionic emission and electron tunneling, becomes a primary leakage path. At a sufficiently low V_dg, our model reduces to the Shockley-Read-Hall theory and thermal generation of electron-hole pairs through traps is dominant