High-gain bipolar transistors with polysilicon tunnel junction emitter contacts

Experimental measurements of the dc gain as a function of temperature and of emitter-base and collector-base current-voltage characteristics for bipolar transistors with polysilicon contacts to the emitter are reported, dc gains as high as 2000 have been measured in devices for which a thin insulating layer was encouraged to grow between the monocrystalline silicon emitter and the polycrystalline silicon contact layer. This gain is 20 times larger than that for devices in which the insulating film growth was inhibited. It is suggested that, for these particular devices, the polysilicon layer contributes to a contact which is very similar to that of a metal-insulator-semiconductor tunnel junction contact. A model based on this hypothesis is developed and shown to give a good fit to all the experimental data.     

Degradation mechanisms in polysilicon emitter bipolar junction transistors for digital applications

This paper is a thorough overview on polysilicon bipolar junction transistors’ (BJTs) reliability, with focus on transistors for digital applications, where the base–emitter junction switches from forward to reverse bias (low fields) and the base–collector junction is reverse biased at high fields. The effects of base–emitter reverse biasing are generation, charging and discharging of traps in silicon oxide or at the Si–SiO₂ interface near the base–emitter junction; their understanding is essential to model transistor current gain degradation and low frequency noise increase. Failure modes and mechanisms, degradation kinetics, lifetime models and physical phenomena related to device aging will be discussed. The base–emitter junction is also stressed by high currents, which lead, for example, to electromigration phenomena. The base–collector junction degradation is mainly due to high field and impact-ionization effects. Reliability constraints are now an important component of a correct design methodology in deep-sub-micron integrated circuits.     

Low frequency noise in complementary npn and pnp polysilicon emitter bipolar junction transistors

Low frequency noise characteristics of high voltage, high performance complementary polysilicon emitter bipolar transistors are described. The influence of the base biasing resistance, emitter geometry and temperature on the noise spectra are discussed. The npn transistors studied exhibited 1/f and shot noise, but the pnp transistors are characterized by significant generation–recombination noise contributions to the total noise. For both types of transistors, the measured output noise is determined primarily by the noise sources in the polysilicon–monosilicon interface. The level of the 1/f noise is proportional to the square of the base current for both npn and pnp transistors. The contribution of the 1/f noise in the collector current is also estimated. The area dependence of 1/f noise in both types of transistors as well as other npn bipolar transistors are presented.     

On the modeling of polysilicon emitter bipolar transistors

In this paper, an attempt is made to derive a general analytical formulation for the current gain and emitter transit time of a polysilicon emitter bipolar transistor (BJT), which includes all previous models as particular cases. Firstly, it is shown that the minority-carrier injection and storage in the polysilicon region can be simply described by effective values of the minority-carrier diffusion length and mobility. These quantities are precisely defined, and depend on the microscopic transport properties of polysilicon grains and grain boundaries. Secondly, a general expression for the effective recombination velocity relative to the poly/mono interface is derived, which includes, and in some cases extends, all previous approaches. This results in a simple and general formulation which avoids some unnecessary simplification present in nearly all previous treatments, and allows easy comparison of the different models for the poly/mono interface and a clear assessment of the relevance of each physical mechanism. Finally, minority-carrier injection and storage in the single-crystal region is addressed. The effect of oxide breakup on both current gain and emitter transit time is also considered, and different models are compared     

Influence of polysilicon deposition on fabrication of power polysilicon emitter bipolar transistors

The aim was to fabricate a polysilicon emitter bipolar transistor for power applications. To this end, different polysilicon deposition steps compatible with the power bipolar technology and their influence on electrical characteristics were studied.<>     

Comparison of experimental and theoretical results on polysilicon emitter bipolar transistors

Two types of polysilicon emitter transistors have been fabricated using identical processing except for the surface treatment prior to polysilicon deposition. The first type was given a dip etch in buffered hydrofluoric acid, which was intended to remove any interfacial oxide, while the second type was given an RCA clean, which was intended to grow an interfacial oxide of known thickness. Detailed electrical measurements have been made on these devices including the temperature dependence of the gain over a wide temperature range. The transistors given an RCA clean have gains approximately five times higher than those given an HF etch. In addition, the temperature dependence of the gain is different for the two types, with the HF devices exhibiting a much stronger dependence at high temperatures than the RCA devices. A detailed comparison is made with the theory and it is shown that the characteristics of the HF devices can largely be explained using a transport theory, while those of the RCA devices can be fully explained using a modified tunneling theory.     

Heterojunction tunnelling model for pnp and npn polysilicon emitter bipolar transistors

A new tunnelling model is described which treats the interfacial layer in a polysilicon emitter transistor as a wide bandgap semiconductor. Potential barriers are formed in the valence and conduction bands, the sizes of which vary with the dopant type and concentration in the interfacial layer.<>     

Effects of rapid thermal processing on the current gain and emitterresistance of polysilicon emitter bipolar transistors

Results of measurements of base current and emitter resistance of polysilicon emitter transistors subjected to different rapid thermal anneal processes of the interfacial layer and different emitter drive-in times are presented. It is shown that a rapid thermal anneal for temperatures on the order of 1050°C leads to devices in which the base current is essentially independent of the emitter drive-in time. The emitter resistance obtained in devices given this interface anneal is considerably lower than that in devices without the anneal, and hence the values obtained are compatible with the requirements for realizing submicrometer bipolar circuits     

1/f noise characterization of base current and emitter interfacialoxide breakup in n-p-n polyemitter bipolar transistors

We propose using base 1/f noise to characterize the distribution of diffusion and tunneling components of base-current (I_b) at the emitter poly/monosilicon interface in n-p-n polyemitter transistors. A noise model is constructed to interpret the I_b 1/f noise (S _iEB) dependence on these combined currents. Measured I_b dependences of S_iEB increase progressively from I_b^1.2 to I_b^2.0 for transistors having emitter structures concomitant with increasing current gains and series emitter resistances ranging between 115-1800 and 7-33Ω, respectively. This is indicative of tunneling components in I_b^2.0 that increase with higher interfacial oxide continuity, and persist in epitaxially realigned emitters     

Investigation of boron diffusion in polysilicon and its applicationto the design of p-n-p polysilicon emitter bipolar transistors withshallow emitter junctions

Ion implantation of boron into undoped polysilicon is utilized. The main goals are to characterize the diffusion of implanted boron from polysilicon, and to correlate the diffusion behavior with the electrical properties of shallow (<500 Å) p-n-p polysilicon emitter bipolar transistors. It is shown that diffusion and electrical activity problems are encountered with boron polysilicon emitters which are not present with arsenic. Base current and emitter resistance are measured on shallow p-n-p polysilicon emitter transistors, and it is shown that the use of a deliberately grown interfacial oxide layer can decrease the base current by a factor of 10 and increase the emitter resistance by a factor of around 2. Comparisons with identical n-p-n polysilicon emitter transistors show that the modeled interfacial oxide, tunneling parameters for n-p-n and p-n-p devices are inconsistent     

Comparison of experimental and computed results on arsenic- and phosphorus-doped polysilicon emitter bipolar transistors

This paper presents a detailed comparison of the measured and computed electrical characteristics of polysilicon emitter bi-polar transistors over a wide range of processing conditions. Detailed electrical measurements are made of both the emitter resistance and the base and collector current as a function of base-emitter voltage. Devices with arsenic- and phosphorus-doped emitters are considered, as well as both with and without a deliberately grown interfacial oxide layer. The theoretical characteristics are computed using a unified model that incorporates both transport and tunneling mechanisms. It is shown that the measured emitter resistances across a wide range of processing conditions can be satisfactorily explained using a tunneling model with a single value for the electron effective barrier height (0.4 eV). Values for the modeling parameters are obtained, in some cases uniquely by measurement, and in others by fitting the experimental results. In devices with a deliberately grown interfacial oxide, the base current is suppressed to such an extent that recombination in the single-crystal emitter and in the base becomes important.     

Decreased low frequency noise by hydrogen passivation of polysilicon emitter bipolar transistors

The effect of hydrogen passivation by forming gas annealing (FGA) on the bipolar junction transistor low frequency noise was investigated. The results demonstrated a reduced 1/f noise component by a factor of five after FGA, which resulted in a reduced corner frequency. An equivalent input noise spectral density (S_IB) dependence on base current (I_B) of S_IBI²_B and on emitter area (A_E) of S_IBA_E⁻¹ was observed, both before and after FGA. The interpretations of the results were (a) the 1/f noise was due to carrier number fluctuation, (b) the noise sources were homogeneously distributed over the polysilicon/monosilicon emitter interfacial oxide, and (c) the noise sources were passivated by hydrogen.     

MODEL AND MODELING OF LOW TEMPERATURE CURRENT GAIN OF POLYSILICON EMITTER BIPOLAR TRANSISTORS

A unified model of low temperature current gain of polysilicon emitter bipolar transistors based on effective recombination method is presented, incorporating band-gap narrowing, carrier freezing-out, tunneling of holes through polysilicon/silicon interface oxide layer and reduced mobility mechanism in polysilicon. The modeling results based on this model are in good agreement with experimental data.     

A comprehensive analytical and numerical model of polysilicon emitter contacts in bipolar transistors

A comprehensive model-both analytical and numerical-is proposed as a tool to analyze heavily doped emitters of transistors with polycrystalline silicon (polysilicon) contacts. The grains and grain boundaries of polysilicon, the interfacial oxide-like layer between polycrystalline and monocrystalline silicon are lumped respectively into "boxes" in which the drift minority current component is neglected. The mobility reduction of carriers in polysilicon on the whole is explicitly attributed to the additional scattering due to the lattice disorder in the grain boundaries and the carrier tunneling through the interface. The effect of the poly-contacts on transistors can be modeled as a reduced surface recombination velocity for minority carriers in combination with a series emitter resistance for majority carriers. Furthermore, by characterizing the monocrystalline emitter with an effective recombination velocity, the effect of the polysilicon layer on the current gain can be analyzed analytically. Computer simulation is used to verify the assumptions of the model formulation. Using published data [1], the analytical and numerical approaches are compared and it is shown that for these devices a unique combination of physical parameters are needed for the model to fit the data.     

A new parameter extraction technique for small-signal equivalentcircuit of polysilicon emitter bipolar transistors

We propose a new parameter extraction method for advanced polysilicon emitter bipolar transistors. This method is based on the predetermination of equivalent circuit parameters using the analytical expressions of de-embedded Z-parameters of these devices. These parameter values are used as initial values for the parameter extraction process using optimization. The entire device equivalent circuit, containing RF probe pad and interconnection circuit parameters extracted by test structures, is optimized to fit measured S-parameters for eliminating de-embedding errors due to the imperfection of pad and interconnection test structures. The equivalent circuit determined by this method shows excellent agreement with the measured S-parameters from 0.1 to 26.5 GHz     

An analytical model for determining carrier transport mechanism of polysilicon emitter bipolar transistors

An analytical model is proposed by including carrier transport mechanisms which previous unified analytical models do not consider: minority carrier combination at both sides of polysilicon-silicon interfacial oxides and thermionic emission over segregation potential barriers for determining the precise carrier transport mechanisms which govern current gain and specific emitter interfacial resistivity. This approach allows us to gain an insight into carrier transport mechanisms and provides a distinct image for polysilicon emitter bipolar devices. With the consideration of the interfacial capture cross section as a function of temperature, the dependence of current gain for devices given an HF etch prior to polysilicon deposition on temperature is first explained successfully. For improving device performance, some directive suggestions are presented.<>     

Physics, technology, and modeling of polysilicon emitter contacts for VLSI bipolar transistors

The physics of minority-carrier injection into polysilicon-contacted emitters has been studied through a series of experiments correlating the base current of the transistor to the structure of the polysilicon/single-crystal silicon interface. Most of the relevant material and processing parameters have been examined. In addition, a novel approach has been taken in the modeling of transport in these emitters to quantify the minority-carrier blocking properties of the polysilicon contacts. Experimental results show that extremely low values of base current can be obtained for devices etched in HF prior to the polysilicon deposition, i.e., devices with only a remnant "native" oxide layer at the polysilicon/single-crystal silicon interface. For these devices, the base current is mainly determined by the recombination and blocking of minority carriers at the polysilicon/monosilicon interface. A number of competing mechanisms exist in several domains of doping, temperature, and time which influence the properties of this interface. One of these mechanisms is the blocking of minority carriers by the native oxide layer itself. The uniformity and, consequently, the blocking characteristics of this layer were found to be strongly affected by the polysilicon doping level and thermal treatment.     

Analysis of transit times and minority carrier mobility in n-p-n 4H-SiC bipolar junction transistors

An analysis of the transit times and minority carrier mobility in n-p-n 4H-SiC RF bipolar junction transistors is presented. These parameters were extracted from small signal RF measurements on 4H-SiC RF transistors with three different base thicknesses: 100, 140, and 200 nm. The study shows that the room temperature minority carrier electron mobility is 215 cm/sup 2//V/spl middot/s for a base Al doping of N/sub B/=4/spl times/10/sup 18/ cm/sup -3/. The analysis reveals that the collector charging time /spl tau//sub C/ and the parasitic charging time /spl tau//sub P/ from the capacitance between metal pads and the underlying collector region have a significant effect on the transistors RF performance. The calculated RF gain is in good agreement with the measured results.     

Effects of emitter edge dislocations on the low frequency noise of silicon planar n-p-n transistors

It is shown that the low-frequency noise in silicon planar n-p-n transistors is affected mainly by the emitter edge dislocations created during emitter phosphorus diffusion.