基于函数级原型的流水线可重构结构的研究

针对目前动态可重构技术中重构时隙的问题,本文利用流水线技术和可熏构技术,提出并讨论一种流水线可重构体系结构的函数级原型设计方法,并采用AES算法对其进行了仿真验证.结果表明,流水线可熏构结构的函数级原型设计方法可有效的解决动态重构系统中的重构时隙问题.     

Transputer网络互连技术探讨

本文讨论利用Transputer构造多计算机并行处理系统的各种方式和实现技术。探讨了靜态网络和可重构网络的构造方法和特点。介绍了InmosC004链路交换器的结构,工作原理、编程方法以及在可重构网络中的使用方法。     

动态可重构系统的通信结构研究

动态可重构技术能在一定控制逻辑的驱动下,对全部或部分逻辑资源实现在系统的动态功能变换和硬件的时分复用.本文介绍了可重构体系结构及典型动态可重构结构;详细分析、比较了动态可重构系统4种通信结构的主要性能,指出各自适用领域,并给出一个应用实例;最后探讨了动态可重构技术研究面临的相关问题和发展趋势.     

FPGA动态可重构理论及其研究进展

近年来,随着微电子技术和计算机技术的发展,尤其是大规模现场可编程门阵列FPGA的出现,实时电路重构技术逐渐成为国际学术界的研究热点;基于FPGA的重构系统具有自适应、自主修复特性,在空间应用中具有非常重要的作用;文章介绍了基于FP-GA动态可重构技术的原理、分类,重点讨论了动态可重构的实现方法及两种技术,并给出了系统重构设计的流程,同时,介绍了基于FPGA动态可重构技术已取得的成功应用,最后展望了FPGA动态可重构技术的发展前景,并指出了有待解决的问题.     

一种面向多核的可重构容错方法

随着二代导航、载人航天、深空探测等空间应用对星载电子产品的低功耗和抗辐射容错能力提出更高的需求,传统多机冗余设计星载计算机面临着亟需进行设计升级换代。将可重构技术应用到多核片上系统的设计中,提出了一种基于动态可重构的容错体系结构,在硬件层提高系统的容错能力和扩展性对未来空间工程应用具有重要意义。首先介绍了多核片上系统和可重构技术的基本概念,简要分析了国际宇航可重构系统的研究案例。随后提出了一种基于动态可重构的容错体系结构,即通过基于系统降级的重构策略来实现系统级容错。在方案验证环节,采用LEON3作为处理单元,对容错模块功能进行了仿真验证。仿真结果表明,容错控制满足预期的设计需求。最后对后续工作做了简要规划,并对可重构容错方法设计进行了总结。     

嵌入式单片自重构平台体系结构的实现

讨论了在Xilinx开发平台上利用FPGA动态重构技术实现自重构系统的方法以及流程。系统中包含静态和动态两种模块,采用Xilinx的基于模块的动态重构设计方法实现。静态模块和动态模块通过一个称为总线宏的结构通信,由嵌入式硬核处理器PPC405控制Xilinx的内部访问接口(ICAP)完成重构。实验表明采用自重构技术可以在单片FPGA上实现复杂的可重构系统。     

MAS中基于任务聚类合同网的自主重构技术*

为了保证嵌入式实时计算系统的可靠性,提出了一种基于多智能体的嵌入式自主重构技术。首先描述了可重构MAS的组织结构,在此基础上,通过对故障节点上的任务进行聚类划分,采用基于任务聚类的合同网协商机制实现任务的再分配,提高系统的并行处理能力;同时,系统为上层用户提供透明的通信机制,屏蔽节点重构对于任务通信的影响,保证对协作式多任务可重构支持。     

AES和SMS4算法的可重构设计与高效实现

分析AES和SMS4算法的原理及可重构性,给出系统的整体结构,综合应用可重构技术、并行处理及流水线技术对算法进行高效实现。与传统设计方案相比,该设计在保证运行速度的同时大大减少了资源的消耗,因此,适用于面积受限且有多种密码需求的安全 系统。     

高速连续数据流记录系统中并行处理接口的研究

为了解决高速数据流的连续记录/读取与存储介质速度慢之间的矛盾,文中用FPGA设计了基于RAID结构的并行处理接口,实现了高速数据的分割降速、合并/恢复、纠错重构,解决了高速数据流连续存储中的I/O瓶颈问题。并行处理接口采用了流水线的设计方式及动态的逻辑配置,使得系统性能得到很大的优化,解决了高速数据处理中的延迟、数据错误、工作时序不同步等问题。并行处理接口最终在实验系统中实现了对高达160MB/S连续实时数据流的处理。     

FPGA动态部分可重构技术概述

可重构计算是一种新的计算结构,它将通用处理器和专用集成电路的优点结合起来,具有灵活、高效的特点。FPGA的动态部分可重构是指在系统运行中对FPGA的部分逻辑资源实现动态的功能变换,从而提高数字系统集成度、增强灵活性、提升容错能力,同时降低成本和功耗。本文主要介绍FPGA动态部分可重构的原理以及实现动态部分可重构的方法,并着重分析4种常用的实现方法;介绍FPGA动态部分可重构技术目前在国内外的最新发展和应用;对FPGA动态部分可重构的未来研究发展方向做简单介绍。      

Dynamic power optimization by exploiting self-reconfiguration in Xilinx Spartan 3-based systems

Reconfigurable architectures are increasingly often applied in various industrial data processing applications, due to the possibility for performing parallel computations and achieving a simplified Systemon-Chip design flow. Furthermore, the exploitation of dynamic and partial hardware reconfiguration has been investigated in different research projects, often in systems based on Xilinx Virtex 2/4 FPGA families, by time-multiplexing hardware resources for multiple functions. This paper describes the exploitation of partial reconfiguration for dynamic power management in a low-power Spartan 3-based level measurement application. The reconfiguration process is thereby applied to optimize system implementation according to the applications requirements on power consumption and performance.     

Dynamic partitioning of multiprocessor systems

Partitioning of processors on a multiprocessor system involves logically dividing the system into processor partitions. Programs can be executed in the different partitions in parallel. Optimally setting the partition size can significantly improve the throughput of multiprocessor systems. The speedup characteristics of parallel programs can be defined by execution signatures. The execution signature of a parallel program on a multiprocessor system is the rate at which the program executes in the absence of other programs and depends upon the number of allocated processors, the specific architecture, and the specific program implementation. Based on the execution signatures, this paper analyzes simple Markovian models of dynamic partitioning. From the analysis, when there are at most two multiprocessor partitions, the optimal dynamic partition size can be found which maximizes throughput. Compared against other partitioning schemes, the dynamic partitioning scheme is shown to be the best in terms of throughput when thereconfiguration overhead is low. If the reconfiguration overhead is high, dynamic partitioning is to be avoided. An expression for the reconfiguration overhead threshold is derived. A general iterative partitioning technique is presented. It is shown that the technique gives maximum throughput forn partions.     

Reconfiguration point decision method based on dynamic complexity for reconfigurable manufacturing system (RMS)

To address the problem of how to identify the best time to implement reconfiguration for the reconfigurable manufacturing system (RMS), a dynamic complexity-based RMS reconfiguration point decision method is proposed. This method first identifies factors that affect RMS dynamic complexity (including both positive and negative complexity) at the machine tool and manufacturing cell levels. Next, based on information entropy theory, a quantitative model for RMS dynamic complexity is created, which is solved via state probability analysis for processing capability and the processing function. This model is combined with cusp catastrophe theory to establish an RMS reconfiguration decision model. Both positive and negative complexity are control variables for cusp catastrophe. Cusp catastrophe’s state condition is used to identify RMS state catastrophe at the final stage of production. This catastrophe point is the RMS reconfiguration point. Finally, the case study result shows that this method can effectively identify the RMS state catastrophe moment so that system reconfiguration is implemented promptly to improve RMS’s responsiveness to the market.     

Dynamic reconfiguration of node location in wormhole networks

Several techniques have been developed to increase the performance of parallel computers. Reconfigurable networks can be used as an alternative to increase the performance. Network reconfiguration can be carried out in different ways. Our research has focused on distributed memory systems with dynamic reconfiguration of node location. Briefly, this technique consists of positioning the processors in the network depending on the existing communication pattern among them, to suit the requirements of each computation.In this article, we present a dynamic reconfiguration technique for wormhole networks. We have used both a crossbar and a multistage interconnection network to implement a reconfigurable logical two-dimensional (2-D) torus topology. The reconfiguration mechanism is based on a distributed reconfiguration algorithm. The algorithm is based on a cost function that requires only local information. We discuss reconfiguration features and adjust the different parameters of the reconfiguration algorithm. We have also studied the deadlock problem in reconfigurable wormhole networks, and give details of our solution. Finally, we have evaluated the performance of this technique under several workloads.     

可重构密码处理结构中重构机制及对性能的影响

重构机制对可重构密码处理系统的性能有着重要的影响,该文从全局、局部、静态、动态几方面提出了流水化可重构密码处理结构中重构机制的分类,给出了各种机制的吞吐率和延迟公式,并分析了几种机制的性能和实现代价,最后给出了在采用局部动态重构机制的可重构密码处理结构中密码处理的性能。     

Reconfiguration and analysis of a fault-tolerant circular butterflyparallel system

The butterfly parallel system has a regular and simple interconnection pattern, making it suitable for VLSI or WSI implementation. The authors propose an effective fault-tolerant technique for the circular butterfly parallel system to ensure its rigid full butterfly structure even in the presence of failures, addressing reconfiguration in detail. The resulting butterfly system has L levels, involves (1/log₂ L)% spare processing elements (PEs), and approximately 50% additional links. The reconfiguration process of the design in response to any operational fault is easy and can be performed in a distributed manner. The reliability and layout of this proposed design are evaluated analytically. This design, due to its specific configuration, exhibits significant improvement in reliability while taking only moderately more layout area     

Dynamic Reconfiguration of Optically Interconnected Networks with Time-Division Multiplexing

Routing performance of optical interconnection networks is limited by both switch complexity and network connectivity. One way to overcome these limitations is to allocate the network bandwidth in a time-division multiplexed (TDM) fashion. With this technique, an appropriate subset of input-to-output connections can be established during a time slot and all possible connections can be established over several time slots. Emulating a fully connected network, however, requires a large multiplexing degree, and thus introduces latencies which may be prohibitive. As a solution, we propose a technique called reconfiguration with time-division multiplexing (RTDM). With RTDM, only a subset, as required by applications, of all possible connections needs to be multiplexed in the network by letting the network go through a sequence of configurations. Network reconfiguration with TDM can be done either statically or dynamically. Static RTDM is applied when communication requirements of an application are known a priori. This paper deals mainly with dynamic RTDM, which requires run time control to accommodate dynamic connection requests. We show that reconfiguration overhead can be amortized over a sequence of configurations. In particular, we describe how the complexity of a dynamic reconfiguration control algorithm can be reduced through pipelined processing of requests. Our simulations show that dynamic RTDM allows for fair and fast allocation of network resources to connection requests. As a result, network service time decreases and communication efficiency increases.     

Experimenting with dynamic linking with ADA

An approach to achieving dynamic reconfiguration within the framework of Ada¹ is described. A technique for introducing a kernel facility for dynamic reconfiguration in Ada is illustrated, and its implementation using the Verdix VADS 5.5 Ada compiling system on a Sun3–120 running the 4.3 BSD Unix operating system is discussed. This experimental kernel allows an Ada program to change its own configuration dynamically, linking new pieces of code at run-time. It is shown how this dynamic facility can be integrated consistently at the Ada language level, without introducing severe inconsistencies with respect to the Standard semantics.     

Shared-nothing并行数据库系统查询优化技术

查询优化是并行数据库系统的核心技术。该文介绍作者自行研制的一个Ｓｈａｒｅｄ－ｎｏｔｈｉｎｇ并行数据库系统ＰＢＡＳＥ／２中独特的两阶段优化策略。为了缩减并行相称优化庞大的搜索空间,ＰＢＡＳＥ／２将并行查询优化划分为顺序优化和并行化两个在阶段。在顺序优化阶段对并行化后的通信代价进行预先估算,将通信开销加入顺序优化的代价模型,同时对动态规划搜索算法进行了修正和扩展,保证了顺序优化阶段得到的最小代价计划在     

可重构并行嵌入式系统

摘要：针对目前应用于军事、航天特殊环境的嵌入式系统存在功能单一、灵活性差、可靠性有限等问题,构建高性能高可靠嵌入式系统RPES,采用SMP并行机制、多种容错策略、硬件支持的软件重注入机制和算法部件动态重构机制,支持系统容错策略以及性能和灵活性的提升。‘测试结果表明,该系统能适应大范围的特殊应用。