匹配滤波器的FPGA实现

本文介绍了匹配滤波器在直接序列扩频通信系统的同步捕获中的应用,研究了数字匹配滤波器的实现方法,提出了基于多相分解的实现结构.与传统的直接实现形式和折叠滤波器等改进形式相比,多相形式具有节省存储空间的优点.     

FIR滤波器的8路多相27子滤波器实现结构

高速FIR滤波器的8路多相直接分解实现结构的工作频率是单路串行实现结构的1/8,计算复杂度是单路串行实现结构的8倍。针对高速FIR滤波器的8路多相直接分解实现结构计算复杂度大这一问题,对FIR滤波器的多相并行实现结构进行了详细推导,提出了FIR滤波器的8路多相27子滤波器实现结构,提出的FIR滤波器的8路多相27子滤波器实现结构的计算复杂度是单路串行实现结构的3.375倍。FPGA实验验证了提出的FIR滤波器的8路多相27子滤波器实现结构的优越性。     

基于脉动阵列结构的高速匹配滤波器设计

文章讨论了高速数传系统中匹配滤波器的设计问题。文中给出了FPGA实现中基于DSP搭建的脉动阵列匹配滤波器架构,同时为了提高滤波器的工作时钟频率,对滤波器进行了多相分解,将高速的串行输入数据降速为多路并行数据进行多相滤波,进一步提升了输入数据时钟频率,为实现高速解调提供了保证。     

一种基于多相滤波器的高速匹配滤波器方法

提出了一种基于多相滤波器的高速匹配滤波器方法,这种方法在滤波器多相分解和整数倍抽取的基础上进行数学推导,不对输入信号做任何处理,仅将多相滤波器组的系数和前后顺序略做调整,即可实现滤波后波形中任意采样点的抽取.不仅具有多相滤波降低运算速率的优点,而且在匹配滤波后不减少采样点的个数,提高后续处理的同步精度.该方法误差小,实现简单,在宽带通信系统中具有良好的应用前景.     

一种简单的直接数字正交变换技术

为了尽可能多地用软件来实现通信接收机的处理功能，需要直接对中频信号进行采样，然后通过数字正交变换的方法得到同相和正交分量。首先对基于多相滤波法的数字正交变换原理进行分析，然后根据多抽样率信号处理理论，详细证明了内插时延滤波器能够用多相滤波器组中的子滤波器实现。     

基于可变带宽EFT滤波器的带宽匹配数字接收方法

该文提出了一种新的基于可变带宽EFT滤波器的带宽匹配数字接收方法。文中利用线性准时不变(LQTI)系统在扩展傅里叶变换(EFT)域的可变带宽频率特性来构建可变带宽滤波器(VBF),并将可变带宽EFT滤波器引入数字下变频(DDC),实现对不同带宽信号的匹配接收。应用这种滤波器的优点在于只有一个直接决定带宽的可调谱参数,更新机制简单。文中还进一步给出带宽匹配接收数字下变频的多相高效结构,运算效率和工程可实现性大大提高。实验结果证明了该方法的正确性和有效性。     

多相并行FIR滤波器的FPGA高速实现方法

L路多相并行FIR滤波器的工作速率是单路串行FIR滤波器的L倍,基于多项式分解的多相并行FIR滤波器实现结构简单、计算复杂度小、滤波运算延迟少;针对多相并行FIR滤波器,给出了基于多项式分解的多相并行FIR滤波器优化实现结构的FPGA高速实现方法。归纳、整理和推导了2路至8路基于多项式分解的多相并行滤波器优化实现结构,并针对FPGA实现的具体特点给出了多相并行滤波器优化实现结构的FPGA高速实现方法。通过测试分析可知,给出的基于多项式分解的多相并行FIR滤波器优化实现结构的FPGA高速实现方法能够在FPGA上高速实现多相并行FIR滤波器。     

4路多相信号半带抽取滤波器优化实现结构

高速FIR滤波器的4路多相实现结构工作的采样速率是单路串行实现结构的4倍,针对4路多相信号半带抽取滤波器直接实现结构计算复杂度大这一问题,提出了一种4路多相信号半带抽取滤波器的优化实现结构。推导得到4路多相信号FIR滤波器优化实现结构;在此基础上,分析不同输出组合的计算复杂度,给出4路多相信号半带抽取滤波器的优化实现结构。对于4路多相信号半带抽取滤波器,仿真结果表明,提出的优化实现结构的计算复杂度约为直接实现结构的75%,验证了其优越性。     

多相抽取滤波器的FPGA实现

信号的多相分解在多抽样率信号处理中有着重要的作用.介绍了多相分解的基本理论,结合FIR抽取滤波器的多相分解形式,用Verilog HDL语言来实现2倍抽取滤波器的多相结构,QuartusⅡ软件仿真输出波形,并且用MATLAB对仿真结果进行验证并作比较.结果正确,最后将编程数据文件下载到FPGA芯片上.多相抽取滤波器的设计方法是可行的,整个设计过程由软件实现,参数易于修改.     

用四端子器件实现的一种新型直接序列扩频匹配滤波器

提出了用四端子器件实现一种新型结构的直接序列扩频匹配滤波器，根据四端子器件的特点，从结构上分析了新型匹配滤波器结构相对于传统的数字匹配滤波器结构的优越性所在，它既保留了传统数字匹配滤波器的低功耗等特点，同时又具有结构简单的特点，大大减少了器件数目，HSPICE的模拟结果及测试芯片的实验结果验证了系统结构设计的可行性。     

Efficient implementation of Koilpillai-Vaidyanathan pseudoquadrature mirror filter (PQMF) banks

An efficient implementation algorithm for the Koilpillai-Vaidyanathan (see ibid., vol.41, no.1, p.82-92, 1993) pseudo quadrature mirror filter (KVPQMF) bank, which is useful in audio compression schemes, is presented. The implementation employs a polyphase system with discrete cosine transforms (DCTs). Theoretical and practical results show a typical saving in computational load of 82% over the direct implementation     

Implementation and perfect reconstruction of a maximally decimatedFIR filter bank using parallel module decomposition

This paper discusses an implementation and the perfect reconstruction (PR) of an M-channel maximally decimated FIR fitter bank. Using the polynomial module arithmetics, the filter bank is decomposed into a set of module filter banks of size M, independent of the filter length. When the filter bank is uniform, the computational cost is the same as the polyphase/FFT implementation. When it is not uniform, in which case the polyphase/FFT implementation is not applicable, the computational cost is still reduced by sharing among channel filtering computations. The parallel module configuration is favorable for hardware implementation because decomposing a large system into small subsystems is generally advantageous for many realizations. The PR analysis is greatly simplified by working on the module filter banks as well     

An Efficient FPGA-based Implementation of Fractional Fourier Transform Algorithm

In this paper, we present an efficient FPGA implementation method of fractional Fourier transform (FrFT) algorithm. Firstly, a polyphase implementation of the FrFT computation algorithm base on the theory of multirate signal processing and filter banks is proposed. This polyphase implementation costs less computations and its parallel structure is suitable for FPGA realization. Then we present one computational method, which improve the resolution on any portion of fractional spectrum. Some realization details, such as the parity restrictions of signal length, special interval for transform order, interpolation filter, continuous frame computation and continuous order computation are also investigated. Finally, the efficiency of the novel method is verified by FPGA implementation results.     

A comparison of hardware implementations of the biorthogonal 9/7 DWT: convolution versus lifting

The filter bank approach for computing the discrete wavelet transform (DWT), which we call the convolution method, can employ either a nonpolyphase or polyphase structure. This work compares filter banks with an alternative polyphase structure for calculating the DWT-the lifting method. We look at the traditional lifting structure and a recently proposed "flipping" structure for implementing lifting. All filter bank structures are implemented on an Altera field-programmable gate array. The quantization of the coefficients (for implementation in fixed-point hardware) plays a crucial role in the performance of all structures, affecting both image compression quality and hardware metrics. We design several quantization methods and compare the best design for each approach: the nonpolyphase filter bank, the polyphase filter bank, the lifting and flipping structures. The results indicate that for the same image compression performance, the flipping structure gives the smallest and fastest, low-power hardware.     

Efficient implementation of uniform filter banks in the absence of critical sampling

It is shown that non-critically-sampled uniform filter banks have an efficient implementation, consisting of an FFT processor, and a time-varying structure derived from the prototype filter polyphase network. It is also shown how DFT filter bank optimisation techniques can be applied in the general case.<>     

A 5-6-GHz polyphase filter with tunable I/Q phase balance

A tunable polyphase filter with integrated input and output buffers was designed and fabricated in a 0.4 /spl mu/m SiGe BiCMOS technology with a 5-6-GHz bandwidth. Series tunable capacitors (varactors) provide phase tunability for the differential quadrature outputs of the polyphase filter. The tunable phase can be used to improve image rejection in Weaver or Hartley architectures, or mitigate in-phase and quadrature (I/Q) phase error in direct conversion or low-IF receivers. The die area of the fabricated circuit with pads is 920 /spl mu/m/spl times/ 755 /spl mu/m. Based on measurements, approximately 15/spl deg/ of I/Q phase imbalance can be tuned out using the fabricated polyphase filter, proving the concept of tunable phase. To the authors' knowledge, this is the first reported tunable I/Q balance polyphase network.     

全数字可配置信道分路技术的设计方法

提出一种全数字可配置信道分路技术的设计方法,是针对多相阵列FFT算法进行的一种串行结构设计,能够按照分路路数灵活配置多相滤波器组和FFT级数,可支持甚至达到上百路的分路路数。对全数字可配置信道分路的设计方法中涉及到的多相滤波器组和FFT两个主要模块的FPGA实现方法进行了详细阐述。基于该设计方法进行了4路、8路和16路信道分路应用的FPGA硬件设计,给出了硬件占用资源情况和误码测试结果,从而证明该设计方法的可实现性。     

一种新的带通信号采样方法

本文提出一种新的带通信号采样方法,实现对带通信号的“等效”低通信号采样。带通信号实际采样率仅为输出端所获同相分量和正交分量采样率的两倍,可以直接确定采样频率和设计低通抗混叠滤波器。该采样方法使用滤波器的多相结构实现,这种实现方法特别适合于线性相移FIR滤波器。     

Restoring Coefficient Symmetry in Polyphase Implementation of Linear-Phase FIR Filters

Polyphase implementation of FIR filters effectively reduces the multiplication rate and data storage in a multirate system. However, the coefficients of the polyphase components are no longer symmetric even though the overall filter has a symmetric (or anti-symmetric) impulse response. In this paper, we introduce a new technique that recasts pairs of the original polyphase components as sums or differences of auxiliary pairs of symmetric and anti-symmetric impulse response filters. The coefficient symmetry of these auxiliary polyphase components can be fully exploited to reduce arithmetic complexity without undue complications. Our new technique makes use of the fact that the impulse responses of the non-symmetric polyphase components exist in time-reversed pairs which can be synthesized from pairs of symmetric and anti-symmetric impulse response filters. This results in a factor-of-two reduction in the number of multipliers required to implement the polyphase components.     

变带宽宽带数字下变频器的设计及其FPGA实现

针对宽带数字接收系统要求处理带宽可变和高度抑制干扰的特点,从传统的基于多相结构的宽带DDC出发,引入窄带DDC中整形滤波的概念,设计了带宽可变、阻带抑制高的变带宽宽带DDC,且在FPGA上实现并验证了其设计的有效性。