A 1-V BiCMOS rail-to-rail amplifier with n-channel depletion modeinput stage

A BiCMOS rail-to-rail operational amplifier capable of operating from supply voltages as low as 1 V is presented. The folded cascode input stage uses an nMOS depletion mode differential pair to provide rail-to-rail common mode voltage range while typically requiring only 40 fA of input bias current. The bipolar transistor differential-to-single-ended conversion network employs a low-voltage base current cancellation technique which provides high input stage voltage gain from a l-V supply yet allows a 3-V/μs slew rate capability. The bipolar transistor output stage uses a low-voltage translinear loop which maintains a low impedance signal path to the output common emitter power devices. This circuit topology enables the amplifier to achieve a 4-MHz bandwidth with 60° of phase margin. The output voltage can swing to within 50 mV of each supply rail. An “on-demand” base current boost technique will be presented which can provide up to 50 mA of output drive capability from a 5-V supply, yet consumes only a few microamps when the output is in the quiescent state. A low voltage level shift technique will be described which uses an n-channel depletion mode source follower to provide isolation between the input and output stages     

A Low-Voltage Quadrature CMOS VCO Based on Voltage-Voltage Feedback Topology

A novel low-voltage quadrature voltage-controlled oscillator (QVCO) with voltage feedback to the input gate of a switching amplifier is proposed and implemented using the standard TSMC 0.18-mum CMOS 1P6M process. The proposed circuit topology is made up of two low-voltage LC-tank VCOs, where the coupled QVCO is obtained using the transformer coupling technique. At the 0.7-V supply voltage, the output phase noise of the VCO is -124.9 dBc/Hz at 1-MHz offset frequency from the carrier frequency of 2.4GHz, and the figure of merit is -185.35dBc/Hz. Total power consumption is 5.18 mW. Tuning range is about 135 MHz while the control voltage was tuned from 0 to 0.7V     

一种基于准浮栅技术的折叠差分结构及其应用

提出了一种基于准浮栅技术的新型折叠差分结构,其偏置电流源的电压降被折叠到输出电压摆幅中,且不受共模输入电压限制而达到较大范围,非常适于低压应用。基于此结构,实现了一种超低压运算放大器。仿真分析表明,该运算放大器能够实现轨到轨(rail-to-rail)的共模输入电压范围和输出电压摆幅,以及较高的共模抑制比。     

Ultra low-voltage CMOS transconductance amplifiers

Simple and symmetrical ultra low-voltage current mode analog circuits and autozeroing amplifiers are presented. The low-voltage analog circuits are based on low-voltage inverters resembling precharge digital logic. Ultra low-voltage analog circuits can be operated at supply voltages down to 250?mV with rail-to-rail input and output swing. The output current of the ultra low-voltage symmetrical transconductance amplifier can be quite large due to a current boost technique. Ultra low-voltage analog circuits can be operated at supply voltages down to 250?mV with rail- to-rail input and output swing. The current headroom is 3???A and the supply voltage is 300?mV. For supply voltages down to 300?mV simulated data shows that the maximum clock frequency is approximately 600?MHz.     

低压低功耗运算放大器结构设计技术

低电压、低功耗、动态摆幅达到轨到轨（Rail—to—Rail）的运放是实现SOC设计的核心，而相关的输入输出模块是其中的关键技术。本文分析了两种分别工作于弱反型区和强反型区的恒跨导Rail—to—Rail输入级，同时给出了低压和极低压下两种AB类控制输出级的实现方案，并对各方案进行了比较和总结。     

Low-voltage pseudo-differential transconductor with improved tunability-linearity trade-off

A new low-voltage pseudo-differential CMOS transconductor using transistors in the saturation region is presented. It keeps the input common-mode voltage constant, while its transconductance is easily tunable through a DC voltage preserving linearity for a moderate range of G/sub m/ values. Post-layout results for a 2.7 V-0.5 /spl mu/m CMOS design dissipating less than 1.5 mW show a 1:2 G/sub m/ tuning range with an almost constant bandwidth over 600 MHz. Total harmonic distortion figures are below -60 dB over the whole range at 10 MHz up to a 100 /spl mu/A/sub p-p/ differential output.     

A High-Quality Rectifier Based on Sheppard–Taylor Converter Operating in Discontinuous Capacitor Voltage Mode

This paper presents a single-phase soft-switched high power factor (PF) Sheppard-Taylor rectifier suitable for applications requiring low-voltage and high-current output. The proposed rectifier is designed to operate at discontinuous capacitor voltage mode. The Sheppard-Taylor converter in this mode of operation provides zero-voltage turnoff switching, as well as natural input PF correction over a wide range of input voltage, which makes the converter suitable for universal input applications. Due to its simplified control circuitry and reduced switch current stress, this converter presents better efficiency and higher reliability. In addition, the presented converter features continuous input-output currents, which result in low electromagnetic interference emission. Principle of operation, theoretical analysis, and experimental results from a laboratory prototype rated at 45 W/10 Vdc output voltage are presented. The measured efficiency and total harmonic distortion of the input line current were 85% and 3.2%, respectively. The input current harmonics meet the EN61000-3-2 Class D requirements.     

一种0.8V衬底驱动轨对轨运算放大器设计

采用衬底驱动技术设计低压低功耗轨对轨运算放大器。输入级采用衬底驱动MOSFET,有效避开阈值电压限制,将电源电压降至0.8V,实现低压下轨对轨共模输入范围。增加衬底驱动冗余差分对及反折式共源共栅求和电路实现恒定跨导控制,消除共模电压对输入级跨导的影响,输出采用前馈式AB类输出级,以提高动态输出电压范围。基于标准0.18μmCMOS工艺仿真运放,测得输出范围0.4～782.5mV,功耗48.8μW,电源抑制比58dB,CMRR65dB,直流开环增益63.8dB,单位增益带宽2.4MHz,相位裕度68°。版图设计采用双阱交叉空铅技术,面积为97.8μm×127.6μm。     

Active input-voltage and load-current sharing in input-series and output-parallel connected modular DC-DC converters using dynamic input-voltage reference scheme

This paper explores a new configuration for modular DC/DC converters, namely, series connection at the input, and parallel connection at the output, such that the converters share the input voltage and load current equally. This is an important step toward realizing a truly modular power system architecture, where low-power, low-voltage, building block modules can be connected in any series/parallel combination at input or at output, to realize any given system specifications. A three-loop control scheme, consisting of a common output voltage loop, individual inner current loops, and individual input voltage loops, is proposed to achieve input voltage and load current sharing. The output voltage loop provides the basic reference for inner current loops, which is modified by the respective input voltage loops. The average of converter input voltages, which is dynamically varying, is chosen as the reference for input voltage loops. This choice of reference eliminates interaction among different control loops. The input-series and output-parallel (ISOP) configuration is analyzed using the incremental negative resistance model of DC/DC converters. Based on the analysis, design methods for input voltage controller are developed. Analysis and proposed design methods are verified through simulation, and experimentally, on an ISOP system consisting of two forward converters.     

Design of a 1-V High-Frequency Bipolar Operational Amplifier

This paper presents the design of a low-voltage high-frequency operational amplifier implemented in bipolar technology. The minimum power supply voltage for this amplifier can be as low as 0.9 V, so it is suitable for portable equipment applications. The design emphasis is on the high frequency response. A pole-zero cancellation compensation technique and a special low-voltage design gives a simulated cutoff frequency of about 175 MHz with a 50° phase margin at a power supply voltage of ±0.5 V with a 10 k load resistance; the low-frequency voltage gain is 110 dB. The common-mode input range includes, and can exceed, the negative supply voltage by about 400 mV. A complimentary class-B type output stage enables the output voltage to reach both supply rails within about 100 mV without significant signal distortion. This amplifier dissipates 875 W.     

Low-Voltage Linearly Tunable CMOS Transconductor With Common-Mode Feedforward

This paper presents a new low-voltage pseudodifferential continuous-time CMOS transconductor for wide-band applications. The proposed cell is based on a feedforward cancellation of the input common-mode signal and keeps the input common mode voltage constant, while the transconductance is easily tunable through a continuous bias voltage. Linearity is preserved during the tuning process for a moderate range of transconductance values. Measurements results for a 0.35-m CMOS design show a 1:2 tuning range with total harmonic distortion figures at 10 MHz below 58 dB over the whole range up to a 200- differential output current. The proposed cell consumes less than 1.1 mW from a single 1.8-V supply.     

Effective parameter extraction using multiple-objective function for VLSI circuits

In this paper an input stage and an output stage are presented for application in low-voltage CMOS operational amplifiers. The input stage operates in strong inversion and has a rail-to-rail common-mode input voltage range. The transconductance (g _m ) is insensitive to the common-mode input voltage. The class AB output stage has a rail-to-rail output range. A class AB control circuit prevents any transistors in the output stage from switching off. This improves the large-signal high-frequency behavior and the step response of the amplifier. A complete two-stage Op Amp employing the proposed input and output stages was realized in a semi-custom CMOS process with minimum channel lengths of 10µm and transistor threshold voltages of approximately 0.7 V. The measured minimum supply voltage is 2.5 V. The measured input voltage range exceeds the supply rails and the output voltage reaches both rails within 130 mV. The unity-gain bandwidth of the complete Op Amp is severely limited by the long channel lengths. Simulations show that a unity-gain bandwidth of 7 MHz is feasible if 2.5µm channel lengths are used.     

Single Transistor High-Impedance Tail Current Source With Extended Common-Mode Input Range and Reduced Supply Requirements

A compact implementation of a single transistor tail current source with very high output impedance (>40 MOmega) and low-voltage requirements is introduced. The tail transistor can operate with less than a drain-source saturation voltage and allows implementation of low-voltage differential pairs with wide common-mode input range and very high common-mode rejection ratio. Simulation and experimental results are shown that validate the proposed circuit.     

Fully-integrated GaAs HBT power amplifier MMIC with high linear output power for 3 GHz-band broadband wireless applications

A high linear output power two-stage GaAs heterojunction bipolar transistor (HBT) power amplifier MMIC is reported. The input, interstage and output matching circuits are designed for wideband and low-voltage operations, and are fully integrated into an MMIC chip. The power amplifier measured with 54 Mbits 64-QAM OFDM signals at a collector supply voltage of 3.3 V showed linear output power of higher than 23.2 dBm at an error vector magnitude of 3.0% in a frequency range 3.3-3.6 GHz     

Circuit techniques for reducing the effects of op-ampimperfections: autozeroing, correlated double sampling, and chopperstabilization

In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input     

一种高阶曲率补偿带隙基准的原理与实现

基于指数型和二阶曲率补偿技术,设计了一个高阶曲率补偿带隙基准.在电路结构上采用电流镜和负反馈回路代替运放反馈回路,不仅避免了运放的失调电压所引起的输出误差和温漂问题,而且使得电路相对简单,更适于电路系统集成.;利用二阶曲率补偿和双极晶体管的电流增益β随温度成指数型变化的规律,对输出电压温度特性进行补偿,提高了的温度稳定性.基于0.6μm BiCMOS工艺设计了基准电路和版图.仿真、测试结果表明:基准在ΔV=2.8V的电源电压幅度范围下,具有0.08mV/V的电源抑制特性.在-55～125℃的范围内Vref的温度系数为5×10-6/℃.     

Low voltage low power 8-bit folding/interpolating ADC with rail-to-rail input range

A new technique for improving the performance of low-voltage folding ADC’s by extending the input range is presented. It is shown that by using both PMOS and NMOS differential pairs in the folding blocks, the overall input voltage range of the ADC can be increased to rail-to-rail. A novel self-adjustment method is also introduced to compensate for the different input–output characteristics of PMOS and NMOS differential pairs. A low voltage 8-bit 80 MSample/s folding/interpolating ADC is then designed and fabricated in a 0.18 μm CMOS process. Operating with a supply voltage as low as 1.2 V, measurements show an INL below ±0.55 LSB, SNDR of 43.5 dB at 80 MHz Sampling Frequency and power dissipation of only 30 mW.     

Three-Mode Dual-Frequency Two-Edge Modulation Scheme for Four-Switch Buck–Boost Converter

Four-switch buck–boost (FSBB) converter features low-voltage stress across the power switches and positive output voltage. They have two active power switches and two synchronous rectifiers, so two freedoms, i.e., the duty cycles of the two active switches, are available to regulate the output voltage. This paper proposes a two-edge modulation (TEM), in which the two active switches are trailing-edge and leading-edge modulated, respectively. Thus, the inductor current ripple can be reduced. Furthermore, a 3-mode TEM is derived to reduce the root-mean-square value of the inductor current to reduce the conduction loss. The line range is divided into three regions, and FSBB operates at boost, buck–boost, and buck modes in the lower, medium, and higher input voltage regions, respectively. At buck and boost modes, only two switches are high-frequency switched, so that the total switching loss is reduced. In the buck–boost mode, the inductor current ripple is very low compared with other two modes. Hence, the switching frequency is lowered to reduce the switching loss. The 3-mode TEM can achieve high efficiency over the line range, which is verified by a 48-V (36–75 V) input, 48-V @ 6.25-A output prototype. The measured efficiency is higher than 96.5% over the line range and the efficiency at the nominal input voltage is 97.8%.      

A 1-V, 8-bit successive approximation ADC in standard CMOS process

A 1-V 8-bit 50-kS/s successive approximation analog-to-digital converter (ADC) implemented in a conventional 1.2-μm CMOS process is presented. Low voltage, large signal swing sample-and-hold, and digital-to-analog conversion are realized based on inverting op-amp configurations with biasing currents added to the op-amp negative input terminal so that the op-amp input common-mode voltages can be biased near ground to minimize the supply voltage. At the same time, the input and output quiescent voltages can be set at half of the supply rails. A low-voltage latched comparator is realized based on the current-mode approach. The entire ADC including all the digital circuits consumes less than 0.34 mW. An effective number of bits of 7.9 was obtained for a 1-kHz 850-mV peak-to-peak input signal     

Some Design Aspects of a Two-Stage Rail-to-Rail CMOS Op Amp

A two-stage low-voltage CMOS op amp with rail-to-rail input and output voltage ranges is presented. The circuit uses complementary differential input pairs to achieve the rail-to-rail common-mode input voltage range. The differential pairs operate in strong inversion, and the constant transconductance is obtained by keeping the sum of the square roots of the tail currents constant. Such an input stage has an offset voltage which depends on the common input voltage level, resulting in a poor common-mode rejection ratio. Therefore, special attention has been given to the reduction of the op amp's systematic offset voltage. Gain-boost amplifiers are connected in a special way to provide not only an increase of the low-frequency open-loop gain, but also to provide a significant reduction of the systematic offset voltage.