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提出了一种基于滤波器组的单载波频域均衡(FB-FDE)技术的窄带干扰抑制方法,该方法在多径时延较大的地空宽带通信中具有很强的窄带干扰抑制能力。从理论上详细分析了基于滤波器组的窄带干扰抑制技术能够克服基于FFT频域均衡缺点的主要原因,并在此基础上提出了基于自适应子带合并的算法。理论分析和仿真试验均表明,该方法抑制窄带干扰能力强,运算简单,适于工程实现。 相似文献
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直接序列扩频系统(Direct Sequence Spread Spectrum,DSSS)自身具有抗窄带干扰的能力,但当存在强窄带干扰时,需要有效的窄带干扰抑制技术来提高系统性能。研究了基于FFT的频域窄带干扰抑制算法,并对其中的加窗、重叠复用及门限生成等关键技术进行了分析。利用Matlab的可视化工具Simulink建立了仿真模型,并在给定的仿真条件下进行了仿真,验证了基于FFT重叠变换的频域陷波技术抑制干扰的有效性,为直接序列扩频系统在干扰环境下的应用提供了依据。 相似文献
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采用可编程门阵列(FPGA)实现FFT算法,增加了信号处理的实时性。针对高速宽带信号的谱分析,提出了一种采用FPGA计算1M点FFT的实现方法,并对运算结果进行了测试验证。该成果同样适用于窄带信号的细微特征分析。 相似文献
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频域LMS算法的TMS320C6701实现 总被引:1,自引:0,他引:1
在直接序列扩频(DSSS)通信系统中,经常需要对窄带干扰进行抑制,但频域LMS算法的运算量限制了它在高速实时系统中的应用。本文介绍了该算法的结构,并且结合TMS320C6000系列DSP的特点,提出了该算法的优化方案。利用DSP的并行运算能力,缩短了FFT和权值更新的运行周期,因此优化后的算法很容易达到实时性。 相似文献
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一种高速实时定点FFT处理器的设计 总被引:21,自引:0,他引:21
本文讨论了采用FPGA和ASIC硬件实现高速实时FFT处理器的设计方案,作者在这种高速FFT设计时选择的特点基于Radix4DIT算法、采用乒乓RAM的设计思路以及级与级间采用流水结构,另外由于FFT基4运算的复杂性,所以在设计基4运算单元、数据通道中串并转换、运算数据的立齐、颠倒位序、双地址发生等方面也有一些特点。整体上考虑是;尽可能地能够进行高速的FFT运算,本文针对1024点、16bits位长、定点数、复数点进行运算;考虑到芯片外围接口的问题,希望外围能够尽量方便用户使用,所以在外围数据、状态和控制线上比较精简,从而把复杂的控制部分转移到芯片内部实现。 相似文献
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针对无线地下传感器网络(Wireless Underground Sensor Network,WUSN)中的信道高路径损耗、信道条件动态变化大和天线尺寸过大等问题,提出一种基于磁感应技术的WUSN收发节点的硬件设计方案。设计了通信系统节点的硬件结构及主控制器和线圈的选型,以及包括天线发射电路、接收电路、程控放大电路和高速A/D采样电路的收发器外围电路,并给出了相关关键参数设计性能指标,搭建了收发通信和性能测试平台。实验结果表明:经FIR滤波器和希尔伯特检波后低频干扰被滤除,降低了误包率,硬件节点满足要求,验证了设计的可行性和可靠性。 相似文献
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In order to demonstrate the practicality of high speed radio LANs, such as HIPERLAN, a hardware demonstrator has been built. To overcome the inter-symbol interference caused by the dispersive nature of the indoor radio channel, a decision feedback equaliser has been included in the system. No central synchronisation is provided in a network and a node must be able to derive all synchronisation from a received packet. This paper describes all of the signal processing hardware built for the demonstrator. The demonstrator is not standards compliant but the physical layer parameters are very similar and the signal processing required in HIPERLAN equipment will be very similar to that in the demonstrator. 相似文献
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A traffic management scheme in serial RapidIO(SRIO) interconnect is proposed to deal with the performance degradation caused by noise and electromagnetic interference(EMI),which is generated by hardly avoidable errors of hardware implementation and tough working environment.The main idea of this scheme includes adaptive speed transition and freeze-acknowledgement(freeze-ACK).Adaptive speed transition can improve throughput and reduce delay in high bit error rate(BER) environment.Simultaneously,freeze-ACK is adopted to conquer frequent usage of feedback channel.Simulation shows that the scheme of combining adaptive speed transition with freeze-ACK offers great performance improvement in SRIO network. 相似文献
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There is considerable interest at present in the design of asynchronous systems based on the use of self-timing components for arithmetic and other operations. Amongst the advantages claimed for asynchronous design are ease of design, high speed, low power, and device speed independence. An often quoted example of the speed improvement possible from self-timed hardware is parallel binary addition, where the carry signals in the worst case must propagate through n stages before the sum can be guaranteed correct. In practice, however, it is not possible to achieve significant speed advantage from the method, and this paper shows that asynchronous adders only give a performance improvement over more conventional hardware in very limited conditions, where the size and regularity of the layout are at a premium 相似文献
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A code-division switch architecture for satellite applications 总被引:2,自引:0,他引:2
This paper introduces a code-division methodology into switching applications. The proposed method is applied in satellite-switched code-division multiple-access (SS/CDMA) systems for routing CDMA traffic channels on board the multibeam satellites. We present code-division switch (CDS) architectures, analyze the CDS performance, and assess its complexity. The CDS has been shown to route CDMA user channels without introducing interference. The proposed CDS architecture is nonblocking, and its hardware complexity and speed are proportional to the size of the switch. We also examine the amplitude distribution of the combined signal in the CDS bus and the interference evaluation of the end-to-end link in the proposed applications. Then we consider the problem of switch control under an optimum or a random algorithm and compare its complexity with the equivalent problem in time-multiplexed switching methods 相似文献
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为了解决超宽带(UWB)高速数据传输中的硬件处理速度瓶颈、码间干扰和多径影响等问题,可采用多个伪码并行调制传输的方法,该方法可以有效提高超宽带系统的传输速率,降低码间干扰和实际工程处理难度。经过对多伪码并行超宽带信号的调制发射、接收解调的性能分析,并通过实物试验,验证了其工程可实现性。与DS-UWB系统相比,在相同的传输带宽下,提高了信息速率,但这是以设备的复杂度增大为代价的。 相似文献
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根据在旋转动力机械设备中扭矩和转速测量的要求,利用现有的电机扭矩转速传感器,设计了一种电机扭矩转速测试仪,实现了电机扭矩、转速的高精度测量。在硬件上,以单片机(R8C/25)作为数据处理核心,采用隔离变压器设计线性直流稳压电源,减少了传统的开关电源供电造成的电磁干扰,且传感器输出信号经高速光耦隔离,提高了系统的抗干扰能力。在软件上,采用定时脉冲计数的方式,利用单片机的事件计数功能和外部中断功能同步对扭矩和转速脉冲信号进行计数,并计算出当前的扭矩值和转速值,进而可计算出轴输出功率,同时将测量值实时动态的显示在数码管上。最终,对传感器进行校验,结果验证了系统设计方案的正确性。 相似文献
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对目标的实时探测与识别是当前干涉式红外成像光谱仪领域研究的热点问题,而光谱仪实时光谱复原是有效解决该问题的前提。利用可见光相机模拟干涉仪而得到干涉图信号,利用高速大容量FPGA芯片设计了一种干涉式红外成像光谱仪实时光谱复原系统。系统主要由干涉图数据预处理、实时光谱复原以及光谱显示等模块组成,以流水线方式运行,能够实时输出目标的光谱信息,具有运算速度快、体积小、便于算法升级等优点,为光谱仪对目标的实时探测与识别研究奠定了良好的技术基础。 相似文献