Analysis of Energy Quantization Effects on Single-Electron Transistor Circuits

In this paper, the effects of energy quantization on different single-electron transistor (SET) circuits (logic inverter, current-biased circuits, and hybrid MOS-SET circuits) are analyzed through analytical modeling and Monte Carlo simulations. It is shown that energy quantization mainly increases the Coulomb blockade area and Coulomb blockade oscillation periodicity, and thus, affects the SET circuit performance. A new model for the noise margin of the SET inverter is proposed, which includes the energy quantization effects. Using the noise margin as a metric, the robustness of the SET inverter is studied against the effects of energy quantization. An analytical expression is developed, which explicitly defines the maximum energy quantization (termed as “ quantization threshold”) that an SET inverter can withstand before its noise margin falls below a specified tolerance level. The effects of energy quantization are further studied for the current-biased negative differential resistance (NDR) circuit and hybrid SETMOS circuit. A new model for the conductance of NDR characteristics is also formulated that explains the energy quantization effects.      

Design of a Robust Analog-to-Digital Converter Based on Complementary SET/CMOS Hybrid Amplifier

As a solution to the high speed, ultralow power, and extremely compact ADC circuit block, a complementary single-electron transistor (SET)/CMOS hybrid amplifier-based analog-to-digital converter (ADC) is proposed. It is implemented with a physics-based SPICE model including nonideal effects in real Si-based SET_s such as the tunnel barrier lowering effect, parasitic MOSFET_s operation, and the phase shift of Coulomb oscillation by the bias of a gate other than a main control gate. Its core scheme is the combination of both the amplification of SET current by MOSFET_s and the suppression of a Coulomb blockade oscillation valley current by the differential amplification. In addition, the transient operation of SET/CMOS hybrid circuit-based ADC_s fully accounting for nonideal effects of real SET_s is successfully demonstrated for the first time. Compared with the previous SET-based ADC_s, our ADC makes features of the immunity to nonideal effects, large voltage swing of the output signal, and high load drivability.     

一种SETMOS二阶带通滤波器设计实现

单电子晶体管（SET）作为一种纳电子器件有着较大的优势,将SET与纳米MOS混合构成的器件（SETMOS）是目前研究的热点之一。SETMOS作为一种新的混合器件,在结合了两者优点的同时,具有与SET一样的库仑振荡特性和MOS高增益等特性。文章基于一种sETM0s混合结构的电压电流特性的数学模型,设计并实现了一种SETMOS二阶带通滤波器,阐述了这种SETMOS带通滤波器的结构、工作条件、性能、参数和特点,并用PSpice对其传输特性进行了仿真验证,结果证明,SETMOS在其通带范围内具有良好的带通幅频特性,且具有低电压、低功耗和高频的特点。     

SOI single-electron transistor with low RC delay for logic cells and SET/FET hybrid ICs

We report on a successful fabrication of silicon-based single-electron transistors (SETs) with low RC time constant and their applications to complementary logic cells and SET/field-effect transistor (FET) hybrid integrated circuit. The SETs were fabricated on a silicon-on-insulator (SOI) structure by a pattern-dependent oxidation (PADOX) technique, combined with e-beam lithography. Drain conductances measured at 4.2 K approach large values of the order of microsiemens, exhibiting Coulomb oscillations with peak-to-valley current ratios /spl Gt/1000. Data analysis with a probable mechanism of PADOX yields their intrinsic speeds of /spl sim/ 2 THz, which is within an order of magnitude of the theoretical quantum limit. Incorporating these SETs as basic elements, in-plane side gate-controlled complementary logic cells and SET/FET hybrid integrated circuits were fabricated on an SOI chip. Such an in-plane structure is very efficient in the Si fabrication process, and the side gates adjacent to the electron island could easily control the phase of Coulomb oscillations. The input-output voltage transfer, characteristic of the logic cell, shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2 K. The SET/FET hybrid integrated circuit consisting of one SET and three FETs yields a high-voltage gain and power amplification with a wide-range output window for driving the next circuit. The small SET input gate voltage of 30 mV is finally converted to 400 mV, corresponding to an amplification ratio of 13.     

A practical SPICE model based on the physics and characteristics of realistic single-electron transistors

A practical model for a single-electron transistor (SET) was developed based on the physical phenomena in realistic Si SETs, and implemented into a conventional circuit simulator. In the proposed model, the SET current calculated by the analytic model is combined with the parasitic MOSFET characteristics, which have been observed in many recently reported SETs formed on Si nanostructures. The SPICE simulation results were compared with the measured characteristics of the Si SETs. In terms of the bias, temperature, and size dependence of the realistic SET characteristics, an extensive comparison leads to good agreement within a reasonable level of accuracy. This result is noticeable in that a single set of model parameters was used, while considering divergent physical phenomena such as the parasitic MOSFET, the Coulomb oscillation phase shift, and the tunneling resistance modulated by the gate bias. When compared to the measured data, the accuracy of the voltage transfer characteristics of a single-electron inverter obtained from the SPICE simulation was within 15%. This new SPICE model can be applied to estimating the realistic performance of a CMOS/SET hybrid circuit or various SET logic architectures.     

A novel SET/MOSFET hybrid static memory cell design

In this paper, a single electron transistor (SET)/metal-oxide-semiconductor field effect transistor (MOSFET)-based static memory cell is proposed. The negative differential conductance (NDC) characteristics of the SET block help us establish the static memory cell circuits more compactly than those in conventional technologies. The proposed memory cell consists of one MOSFET and two back-to-back connected SET blocks exhibiting the NDC. The peak-to-valley current ratio of the SET block is above four with C/sub G/=5.4C/sub T/ (C/sub T/=0.1 aF) at T=77K. The read and write operations of the proposed memory cell were validated with SET/MOSFET hybrid simulations at T=77 K. Even though the fabrication process that integrates MOSFET devices and SET blocks with NDC is not yet available, these results suggest that the proposed SET/MOSFET hybrid static memory cell is suitable for a high-density memory system.     

Observation of negative differential resistance and single-electron tunneling in electromigrated break junctions

We observed a negative differential resistance (NDR) along with single-electron tunneling (SET) in the electron transport of electromigrated break junctions with metal-free tetraphenylporphyrin (H₂BSTBPP) at a temperature of 11 K. The NDR strongly depended on the applied gate voltages, and appeared only in the electron tunneling region of the Coulomb diamond. We could explain the mechanism of this new type of electron transport by a model assuming a molecular Coulomb island and local density of states of the source and the drain electrodes.     

Using post-breakdown conduction study in a MIS structure to better understand the resistive switching mechanism in an MIM stack

We apply our understanding of the physics of failure in the post-breakdown regime of high-κ dielectric-based conventional logic transistors having a metal-insulator-semiconductor (MIS) structure to interpret the mechanism of resistive switching in resistive random-access memory (RRAM) technology metal-insulator-metal (MIM) stacks. Oxygen vacancies, gate metal migration and metal filament formation in the gate dielectric which constitute the chemistry of breakdown in the post-breakdown stage of logic gate stacks are attributed to be the mechanisms responsible for the SET process in RRAM technology. In this paper, we draw an analogy between the breakdown study in logic devices and filamentation physics in resistive non-volatile memory.     

Accurate and computer efficient modelling of single event transients in CMOS circuits

A new analytical modelling approach to evaluate the impact of single event transients (SETs) on CMOS circuits has been developed. The model allows evaluation of transient pulse amplitude and width (duration) at the logic level, without the need to run circuit level (Spice-like) simulations. The SET mechanism in MOS circuits is normally investigated by Spice-like circuit simulation. The problem is that electrical simulation is time-consuming and must be performed for each different circuit topology, incident particle and track. The availability of a simple model at the logic gate level may greatly improve circuit sensitivity analysis. The electrical response of a circuit to an ionising particle hit depends on many parameters, such as circuit topology, circuit geometry and waveform shape of the charge injection mechanism. The proposed analytical model, which is accurate and computer efficient, captures these transistor-level effects of ionising particle hits and models them to the logic level of abstraction. The key idea is to exploit a model that allows the rapid determination of the sensitivity of any logic gate in a CMOS circuit, without the need to run circuit simulations. The model predicts whether or not a particle hit generates a SET, which may propagate to the next logic gate or memory element, making possible to analyse the sensitivity of each node in a complex circuit. Model derivation is strongly related to circuit electrical behaviour, being consistent with technology scaling. The model is suitable for integration into CAD tools, intending to make automated evaluation of circuit sensitivity to SET possible, as well as automated estimation of soft error rate     

Silicon single electron transistors with SOI and MOSFET structures: the role of access resistances

Coulomb blockade has been widely reported in silicon and metallic structures without intentional tunnel barriers. In particular, a simple constriction in silicon-on-insulator (SOI) allows to build a three-terminal silicon single-electron transistor (SET) operating at moderate temperature. The key parameters are the access resistances confining the electrons and the size of the gate-channel overlap, which sets the Coulomb energy. Thin films of doped silicon with sheet resistance of a few tens of h/e/sup 2/ are well suited for fabricating optimized access resistances. Low doped extensions with typical resistivity 1000 /spl Omega//spl mu/m (at 300 K) are also good candidates. We illustrate this MOS-SET principle in SOI constriction and standard MOSFET of similar size. Although relying on different concepts, the ultimate MOSFET and MOS-SET are shown to be technologically close, differing mostly by the ratio between the channel resistance over the access resistance. Because this ratio is decreasing as the gate length shrinks, single electron effects should become more and more important at high temperature in the subthreshold regime of standard field effect transistor devices.     

Coulomb Blockade Peak Statistics Influenced by Background Charge Configuration

Statistics of Coulomb blockade oscillations in metallic singleelectron transistors are investigated. We observe stronglynon-Gaussian distributions of nearest-neighbor conductancepeak spacings. The fluctuations of peak position are found tobe reproducible as a function of gate voltage, with ahysteresis when sweeping the voltage up and down. Our resultsare explained in terms of gate potential dependentbistabilities in the background charge configuration. Weemphasize the importance of carefully taking into account theenvironmental charge fluctuations in high sensitivityelectrometric SET experiments, like such on single particlelevel statistics in semiconductor quantum dots.     

Single electron encoded latches and flip-flops

Single electron tunneling (SET) technology offers the ability to control the transport of individual electrons. In this paper, we investigate single electron encoded logic (SEEL) memory circuits, in which the Boolean logic values are encoded as zero or one electron charges. More specifically, we focus on the implementation of SEEL latches and flip-flops. All proposed circuits are verified by means of simulation using the SIMulation Of Nanostructures package. We first present a generic SEEL linear threshold gate implementation, from which we derive a family of Boolean logic gates. Second, we propose Boolean gate-based implementations of the RS latch, the D latch, and D flip-flop. Third, we propose threshold gate-based implementations of the same memory elements. Finally, we discuss the estimated area, delay, and power consumption of the Boolean gate-based and threshold gate-based implementations, and compare them with other SET-based memory elements.     

Observation of room temperature negative differential resistance in multi-layer heterostructures of quantum dots and conducting polymers

Multi-layer heterostructure negative differential resistance devices based on poly-[2-methoxy-5-(2'-ethyl-hexyloxy)-1,4-phenylenevinylene] (MEH-PPV) conducting polymer and CdSe quantum dots is reported. The conducting polymer MEH-PPV acts as a barrier while CdSe quantum dots form the well layer. The devices exhibit negative differential resistance (NDR) at low voltages. For these devices, strong negative differential resistance is observed at room temperature. A maximum value of 51 for the peak-to-valley ratio of current is reported. Tunneling of electrons through the discrete quantum confined states in the CdSe quantum dots is believed to be responsible for the multiple peaks observed in the I-V measurement. Depending on the observed NDR signature, operating mechanisms are explored based on resonant tunneling and Coulomb blockade effects.     

Hybrid Flexible Resistive Random Access Memory‐Gated Transistor for Novel Nonvolatile Data Storage

Here, a single‐device demonstration of novel hybrid architecture is reported to achieve programmable transistor nodes which have analogies to flash memory by incorporating a resistive switching random access memory (RRAM) device as a resistive switch gate for field effect transistor (FET) on a flexible substrate. A high performance flexible RRAM with a three‐layered structure is fabricated by utilizing solution‐processed MoS₂ nanosheets sandwiched between poly(methyl methacrylate) polymer layers. Gate coupling with the pentacene‐based transistor can be controlled by the RRAM memory state to produce a nonprogrammed state (inactive) and a programmed state (active) with a well‐defined memory window. Compared to the reference flash memory device based on the MoS₂ floating gate, the hybrid device presents robust access speed and retention ability. Furthermore, the hybrid RRAM‐gated FET is used to build an integrated logic circuit and a wide logic window in inverter logic is achieved. The controllable, well‐defined memory window, long retention time, and fast access speed of this novel hybrid device may open up new possibilities of realizing fully functional nonvolatile memory for high‐performance flexible electronics.     

Single-electron transistors based on gate-induced Si island for single-electron logic application

The island size dependence of the capacitance components of single-electron transistors (SETs) based on gate-induced Si islands was extracted from the electrical characteristics. In the fabricated SETs, the sidewall gate tunes the electrically induced tunnel junctions, and controls the phase of the Coulomb oscillation. The capacitance between the sidewall gate and the Si island extracted from the Coulomb oscillation phase shift of the SETs with sidewall depletion gates on a silicon-on-insulator nanowire was independent of the Si island size, which is consistent with the device structure. The Coulomb oscillation phase shift of the fabricated SETs has the potential for a complementary operation. As a possible application to single-electron logic, the complementary single-electron inverter and binary decision diagram operation on the basis of the Coulomb oscillation phase shift and the tunable tunnel junctions were demonstrated.     

Valley blockade quantum switching in Silicon nanostructures

In analogy to the Coulomb and the Pauli spin blockade, based on the electrostatic repulsion and the Pauli exclusion principle respectively, the concept of valley blockade in Silicon nanostructures is explored. The valley parity operator is defined. Valley blockade is determined by the parity conservation of valley composition eigenvectors in quantum transport. A Silicon quantum changeover switch based on a triple of donor quantum dots capable to separate electrons having opposite valley parity by virtue of the valley parity conservation is proposed. The quantum changeover switch represents a novel kind of hybrid quantum based classical logic device.     

Coulomb blockade induced negative differential resistance effect in a self-assembly Si quantum dots array at room temperature

We report a Coulomb blockade induced negative differential resistance (NDR) effect at room temperature in a self-assembly Si quantum dots (Si-QDs) array (Al/SiO₂/Si-QDs/SiO₂/p-Si), which is fabricated in a plasma enhanced chemical vapor deposition system by using layer-by-layer deposition and in-situ plasma oxidation techniques. Obvious NDR effects are directly observed in the current-voltage characteristics, while corresponding capacitance peaks are also identified at the same voltage positions in the capacitance-voltage characteristics. The NDR effect in dot array, arising from the Coulomb blockade effect in the nanometer-sized Si-QDs, exhibits distinctive scan-rate and scan-direction dependences and differs remarkably from that in the quantum well structure in the formation mechanism. Better understanding of the observed NDR effect in Si-QDs array is obtained in a master-equation-based numerical model, where both the scan-rate and scan-direction dependences are well explained.     

3-D Design and Analysis of Functional NEMS-gate MOSFETs and SETs

Nanoelectromechanical system (NEMS)-gate metal- oxide-semiconductor field effect transistor (MOSFET) and single- electron transistor (SET) structures are investigated by combining 3-D design and SPICE simulation. First, the metal gate is simulated by using a 3-D simulator, which enables to design realistic 3-D device structures, and its movement is studied for different design parameters. It is demonstrated that a low stiffness design of the structure is essential for a low-voltage actuation. Results are compared with theoretical numerical simulation and a tunable capacitor model is then embedded in a SPICE simulator and coupled either with a transistor model for MOS-NEMS or with a newly developed SET analytical model for SET-NEMS. It is shown that the use of NEMS membrane can add new functionalities to conventional MOSFET and SET, such as very abrupt switching of the current, which can break theoretical limits of MOSFET, or modulation of Coulomb oscillations governing SET characteristics     

Single electron transistor fabricated with SOI wafer

The single electron transistor (SET) is the most sensitive device for measuring the charge of electron. It has been proposed by Kane that the SET can be used for readout of calculated results in Si-based quantum computer. We fabricated the SET with SOI substrate utilizing the suspended mask of SiO₂ and Si for the purpose of using it for readout of calculation in Si-Based quantum computer. By using only the above materials for the mask, high temperature processes including ion implantation and activation annealing could be possible and it was never achieved in conventional methods with the suspended mask with photoresist. First, the suspended mask with enough undercut in SOI was made by removing the box oxide of SOI wafer combining with pattern delineation by electron beam lithography, anisotropically reactive ion etching and isotropic wet etching. After forming the suspended mask, Al films were evaporated from two different angles to make an overlap just below the bridge, resulting in completing the SET in the undercut region possible to measure the electron spin. After making the Al/Al₂O₃/Al SET, we measured the I–V characteristic between source and drain at 1.8 K. The Coulomb blockade and the Coulomb oscillation were observed.